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* send START condition (also as REPEATED START condition)
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* send START condition (also as REPEATED START condition)
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* send STOP condition
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* send STOP condition
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* send (at least) one byte while also sampling one byte from the bus
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* send (at least) one byte while also sampling one byte from the bus
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[TIP]
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A transmission can be terminated at any time by disabling the TWI module
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by clearing the _TWI_CTRL_EN_ control register bit.
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[IMPORTANT]
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[IMPORTANT]
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The serial clock (SCL) and the serial data (SDA) lines can only be actively driven low by the
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The serial clock (SCL) and the serial data (SDA) lines can only be actively driven low by the
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controller. Hence, external pull-up resistors are required for these lines.
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controller. Hence, external pull-up resistors are required for these lines.
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The TWI clock frequency is defined via the 3-bit _TWI_CTRL_PRSCx_ clock prescaler. The following prescalers
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The TWI clock frequency is defined via the 3-bit _TWI_CTRL_PRSCx_ clock prescaler. The following prescalers
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`)
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`)
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**Interrupt**
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**Interrupt**
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The TWI module provides a single interrupt to singal _idle state_ (= read for new transmission) to the CPU. Whenever TWI SPI module
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The TWI module provides a single interrupt to signal _idle state_ (= read for new transmission) to the CPU. Whenever TWI SPI module
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is currently idle (and enabled), the interrupt request is active. A pending interrupt request is cleared
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is currently idle (and enabled), the interrupt request is active. A pending interrupt request is cleared
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by triggering a new TWI transmission or by disabling the device.
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by triggering a new TWI transmission or by disabling the device.
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.TWI register map (`struct NEORV32_TWI`)
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.TWI register map (`struct NEORV32_TWI`)
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