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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Keeper (BUSKEEPER) >> #
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-- # << NEORV32 - Bus Keeper (BUSKEEPER) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This unit monitors the processor-internal bus. If the accessed INTERNAL (IMEM if enabled, #
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-- # This unit monitors the processor-internal bus. If the accessed module does not respond within #
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-- # DMEM if enabled, BOOTROM + IO region) module does not respond within the defined number of #
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-- # the defined number of cycles (VHDL package: max_proc_int_response_time_c) or issues an ERROR #
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-- # cycles (VHDL package: max_proc_int_response_time_c) the BUS KEEPER asserts the error signal #
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-- # conditions the BUS KEEPER asserts the error signal to inform the CPU. #
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-- # to inform the CPU / bus driver. #
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-- # #
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-- # WARNING: The bus keeper timeout does not track accesses via the processor-external bus #
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-- # interface! If the timeout-function of the Wishbone interface is not used, the CPU #
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-- # might be permanently stalled by an an unacknowledged transfer! If the external bus #
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-- # interface is disabled, ALL accesses by the CPU are internal. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_bus_keeper is
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entity neorv32_bus_keeper is
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generic (
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-- External memory interface --
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MEM_EXT_EN : boolean; -- implement external memory bus interface?
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-- Internal instruction memory --
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MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
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-- Internal data memory --
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MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural -- size of processor-internal data memory in bytes
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);
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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-- bus monitoring --
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-- bus monitoring --
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bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
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bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
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bus_rden_i : in std_ulogic; -- read enable
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bus_rden_i : in std_ulogic; -- read enable
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bus_wren_i : in std_ulogic; -- write enable
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bus_wren_i : in std_ulogic; -- write enable
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bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
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bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
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bus_err_i : in std_ulogic -- transfer error from bus system
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bus_err_i : in std_ulogic; -- transfer error from bus system
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bus_tmo_i : in std_ulogic; -- transfer timeout (external interface)
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bus_ext_i : in std_ulogic -- external bus access
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);
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);
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end neorv32_bus_keeper;
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end neorv32_bus_keeper;
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architecture neorv32_bus_keeper_rtl of neorv32_bus_keeper is
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architecture neorv32_bus_keeper_rtl of neorv32_bus_keeper is
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(buskeeper_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(buskeeper_size_c); -- low address boundary bit
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-- Control register --
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-- Control register --
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constant ctrl_err_type_c : natural := 0; -- r/-: error type: 0=device error, 1=access timeout
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constant ctrl_err_type_c : natural := 0; -- r/-: error type: 0=device error, 1=access timeout
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constant ctrl_err_src_c : natural := 1; -- r/-: error source: 0=processor-external, 1=processor-internal
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constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero
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constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero
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-- sticky error flag --
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-- sticky error flags --
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signal err_flag : std_ulogic;
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signal err_flag : std_ulogic;
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signal err_type : std_ulogic;
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- word write enable
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- read enable
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signal rden : std_ulogic; -- read enable
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-- bus access check --
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type access_check_t is record
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int_imem : std_ulogic;
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int_dmem : std_ulogic;
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int_bootrom_io : std_ulogic;
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valid : std_ulogic;
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end record;
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signal access_check : access_check_t;
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-- controller --
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-- controller --
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type control_t is record
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type control_t is record
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pending : std_ulogic;
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pending : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(max_proc_int_response_time_c)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(max_proc_int_response_time_c)-1 downto 0);
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err_type : std_ulogic;
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err_type : std_ulogic;
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int_ext : std_ulogic;
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bus_err : std_ulogic;
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bus_err : std_ulogic;
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end record;
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end record;
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signal control : control_t;
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signal control : control_t;
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begin
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begin
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = buskeeper_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = buskeeper_base_c(hi_abb_c downto lo_abb_c)) else '0';
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wren <= acc_en and wren_i;
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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rden <= acc_en and rden_i;
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-- Bus Access Check -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- access to processor-internal IMEM or DMEM? --
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access_check.int_imem <= '1' when (bus_addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_EN = true) else '0';
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access_check.int_dmem <= '1' when (bus_addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0';
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-- access to processor-internal BOOTROM or IO devices? --
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access_check.int_bootrom_io <= '1' when (bus_addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
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-- actual internal bus access? --
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access_check.valid <= access_check.int_imem or access_check.int_dmem or access_check.int_bootrom_io;
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= wren or rden;
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ack_o <= wren or rden;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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data_o(ctrl_err_type_c) <= control.err_type;
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data_o(ctrl_err_type_c) <= err_type;
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data_o(ctrl_err_src_c) <= control.int_ext;
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data_o(ctrl_err_flag_c) <= err_flag;
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data_o(ctrl_err_flag_c) <= err_flag;
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end if;
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end if;
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--
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--
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if (control.bus_err = '1') then
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if (control.bus_err = '1') then -- sticky error flag
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err_flag <= '1'; -- sticky error flag
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err_flag <= '1';
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elsif (rden = '1') then -- clear on read
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err_type <= control.err_type;
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elsif ((wren or rden) = '1') then -- clear on or read or write
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err_flag <= '0';
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err_flag <= '0';
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err_type <= '0';
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end if;
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end if;
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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control.pending <= '0';
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control.pending <= '0';
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control.bus_err <= '0';
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control.bus_err <= '0';
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control.err_type <= def_rst_val_c;
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control.err_type <= def_rst_val_c;
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control.int_ext <= def_rst_val_c;
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control.timeout <= (others => def_rst_val_c);
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control.timeout <= (others => def_rst_val_c);
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err_o <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- defaults --
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-- defaults --
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control.bus_err <= '0';
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control.bus_err <= '0';
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-- access monitor: IDLE --
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-- access monitor: IDLE --
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if (control.pending = '0') then
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if (control.pending = '0') then
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control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)));
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control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)));
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if (bus_rden_i = '1') or (bus_wren_i = '1') then
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if (bus_rden_i = '1') or (bus_wren_i = '1') then
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if (access_check.valid = '1') or (MEM_EXT_EN = false) then
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control.int_ext <= '1'; -- processor-internal access
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else
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control.int_ext <= '0'; -- processor-external access
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end if;
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control.pending <= '1';
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control.pending <= '1';
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end if;
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end if;
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-- access monitor: PENDING --
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-- access monitor: PENDING --
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else
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else
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control.timeout <= std_ulogic_vector(unsigned(control.timeout) - 1); -- countdown timer
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control.timeout <= std_ulogic_vector(unsigned(control.timeout) - 1); -- countdown timer
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if (bus_ack_i = '1') then -- normal termination by bus system
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if (bus_err_i = '1') then -- error termination by bus system
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control.err_type <= '0'; -- don't care
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control.bus_err <= '0';
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control.pending <= '0';
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elsif (bus_err_i = '1') then -- error termination by bus system
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control.err_type <= '0'; -- device error
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control.err_type <= '0'; -- device error
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control.bus_err <= '1';
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control.bus_err <= '1';
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control.pending <= '0';
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control.pending <= '0';
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elsif (or_reduce_f(control.timeout) = '0') and (control.int_ext = '1') then -- timeout! terminate bus transfer (internal accesses only!)
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elsif ((or_reduce_f(control.timeout) = '0') and (bus_ext_i = '0')) or -- internal access timeout
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(bus_tmo_i = '1') then -- external access timeout
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control.err_type <= '1'; -- timeout error
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control.err_type <= '1'; -- timeout error
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control.bus_err <= '1';
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control.bus_err <= '1';
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control.pending <= '0';
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control.pending <= '0';
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elsif (bus_ack_i = '1') then -- normal termination by bus system
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control.err_type <= '0'; -- don't care
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control.bus_err <= '0';
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control.pending <= '0';
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end if;
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end if;
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end if;
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end if;
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-- only output timeout errors here - device errors are already propagated by the bus system --
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err_o <= control.bus_err and control.err_type;
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end if;
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end if;
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end process keeper_control;
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end process keeper_control;
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-- signal bus error to CPU --
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err_o <= control.bus_err;
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end neorv32_bus_keeper_rtl;
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end neorv32_bus_keeper_rtl;
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