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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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TINY_SHIFT_EN : boolean := false; -- use tiny (single-bit) shifter for shift operations
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TINY_SHIFT_EN : boolean := false; -- use tiny (single-bit) shifter for shift operations
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
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firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
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firq_ack_o : out std_ulogic_vector(15 downto 0)
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firq_ack_o : out std_ulogic_vector(15 downto 0);
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-- debug mode (halt) request --
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db_halt_req_i : in std_ulogic := '0'
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);
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);
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end neorv32_cpu;
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end neorv32_cpu;
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architecture neorv32_cpu_rtl of neorv32_cpu is
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architecture neorv32_cpu_rtl of neorv32_cpu is
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-- U-extension requires Zicsr extension --
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-- U-extension requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- Instruction prefetch buffer size --
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-- Instruction prefetch buffer size --
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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-- A extension - only lr.w and sc.w are supported yet --
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assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
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-- A extension - only lr.w and sc.w are supported --
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assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG NOTE. Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity note;
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-- FIXME: Bit manipulation warning --
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-- FIXME: Bit manipulation warning --
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assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
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assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
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-- Co-processor timeout counter (for debugging only) --
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-- Co-processor timeout counter (for debugging only) --
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assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
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assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
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-- PMP regions check --
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-- PMP regions check --
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assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
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assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
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-- PMP granulartiy --
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-- PMP granularity --
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assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
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assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
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assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 8 bytes." severity error;
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assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 8 bytes." severity error;
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-- PMP notifier --
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-- PMP notifier --
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assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(PMP_NUM_REGIONS) & " regions and a minimal granularity of " & integer'image(PMP_MIN_GRANULARITY) & " bytes." severity note;
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assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(PMP_NUM_REGIONS) & " regions and a minimal granularity of " & integer'image(PMP_MIN_GRANULARITY) & " bytes." severity note;
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-- PMP requires Zicsr extension --
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-- PMP requires Zicsr extension --
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-- HPM counters notifier --
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-- HPM counters notifier --
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assert not (HPM_NUM_CNTS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & integer'image(HPM_NUM_CNTS) & " HPM counters (each " & integer'image(HPM_CNT_WIDTH) & "-bit wide)." severity note;
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assert not (HPM_NUM_CNTS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & integer'image(HPM_NUM_CNTS) & " HPM counters (each " & integer'image(HPM_CNT_WIDTH) & "-bit wide)." severity note;
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-- HPM CNT requires Zicsr extension --
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-- HPM CNT requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors (HPM) require <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors (HPM) require <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- Debug mode --
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assert not (CPU_EXTENSION_RISCV_DEBUG = true) report "NEORV32 CPU CONFIG NOTE: Implementing RISC-V DEBUG MODE extension." severity note;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- FIXME: debug mode extension warning --
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assert not (CPU_EXTENSION_RISCV_DEBUG = true) report "NEORV32 CPU CONFIG WARNING! RISC-V DEBUG MODE extension <CPU_EXTENSION_RISCV_DEBUG> is still EXPERIMENTAL." severity warning;
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: neorv32_cpu_control
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neorv32_cpu_control_inst: neorv32_cpu_control
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generic map (
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generic map (
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-- General --
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-- General --
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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CPU_DEBUG_ADDR => CPU_DEBUG_ADDR, -- cpu debug mode start address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- FPU interface --
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-- FPU interface --
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fpu_rm_o => fpu_rm, -- rounding mode
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fpu_rm_o => fpu_rm, -- rounding mode
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fpu_flags_i => fpu_flags, -- exception flags
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fpu_flags_i => fpu_flags, -- exception flags
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-- debug mode (halt) request --
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db_halt_req_i => db_halt_req_i,
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i => msw_irq_i, -- machine software interrupt
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msw_irq_i => msw_irq_i, -- machine software interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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-- non-maskable interrupt --
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-- non-maskable interrupt --
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