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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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generic (
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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TINY_SHIFT_EN : boolean := false -- use tiny (single-bit) shifter for shift operations
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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if (shifter.start = '1') then -- trigger new shift
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if (shifter.start = '1') then -- trigger new shift
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shifter.sreg <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.sreg <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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elsif (shifter.run = '1') then -- running shift
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elsif (shifter.run = '1') then -- running shift
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-- coarse shift: multiples of 4 --
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-- coarse shift: multiples of 4 --
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if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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if (TINY_SHIFT_EN = false) and -- use coarse shifts first if TINY SHIFT option is NOT enabled
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(or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
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shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
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else -- SRL: shift right logical / SRA: shift right arithmetical
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
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end if;
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end if;
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-- fine shift: single shifts, 0..3 times --
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-- fine shift: single shifts, 0..3 times; use ONLY single-bit shifts if TINY_SHIFT_EN is enabled (even smaller than the default approach) --
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else
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else
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
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shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
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else -- SRL: shift right logical / SRA: shift right arithmetical
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else -- SRL: shift right logical / SRA: shift right arithmetical
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