| Line 58... |
Line 58... |
rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- operands --
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-- operands --
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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--
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- co-processor arbiter and interface --
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-- co-processor arbiter and interface --
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type cp_ctrl_t is record
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type cp_ctrl_t is record
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cmd : std_ulogic;
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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| Line 117... |
Line 116... |
cmp_o <= cmp;
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cmp_o <= cmp;
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-- ALU Input Operand Mux ------------------------------------------------------------------
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-- ALU Input Operand Mux ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opa <= pc_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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-- Binary Adder/Subtracter ----------------------------------------------------------------
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-- Binary Adder/Subtracter ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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begin
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begin
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-- operand sign-extension --
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-- operand sign-extension --
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op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
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op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
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op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
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op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
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-- add/sub(slt) select --
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-- add/sub(slt) select --
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if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction
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if (ctrl_i(ctrl_alu_op0_c) = '1') then -- subtraction
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op_y_v := not op_b_v;
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op_y_v := not op_b_v;
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cin_v(0) := '1';
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cin_v(0) := '1';
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else -- addition
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else -- addition
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op_y_v := op_b_v;
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op_y_v := op_b_v;
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cin_v(0) := '0';
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cin_v(0) := '0';
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end if;
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end if;
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-- adder core (result + carry/borrow) --
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-- adder core --
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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end process binary_arithmetic_core;
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end process binary_arithmetic_core;
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-- direct output of address result --
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-- direct output of adder result --
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add_o <= addsub_res(data_width_c-1 downto 0);
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add_o <= addsub_res(data_width_c-1 downto 0);
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-- ALU arithmetic logic core --
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arithmetic_core: process(ctrl_i, addsub_res)
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-- ALU Operation Select -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_core: process(ctrl_i, addsub_res, rs1_i, opb)
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begin
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begin
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if (ctrl_i(ctrl_alu_arith_c) = alu_arith_cmd_addsub_c) then -- ADD/SUB
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case ctrl_i(ctrl_alu_op2_c downto ctrl_alu_op0_c) is
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arith_res <= addsub_res(data_width_c-1 downto 0);
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when alu_op_add_c => alu_res <= addsub_res(data_width_c-1 downto 0); -- (default)
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else -- SLT
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when alu_op_sub_c => alu_res <= addsub_res(data_width_c-1 downto 0);
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arith_res <= (others => '0');
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-- when alu_op_mova_c => alu_res <= rs1_i; -- FIXME
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arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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when alu_op_slt_c => alu_res <= (others => '0'); alu_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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end if;
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when alu_op_movb_c => alu_res <= opb;
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end process arithmetic_core;
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when alu_op_xor_c => alu_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_op_or_c => alu_res <= rs1_i or opb;
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when alu_op_and_c => alu_res <= rs1_i and opb;
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when others => alu_res <= addsub_res(data_width_c-1 downto 0);
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end case;
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end process alu_core;
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, alu_res, pc2_i, csr_i, cp_res)
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begin
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case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
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when alu_func_core_c => res_o <= alu_res; -- (default)
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when alu_func_nxpc_c => res_o <= pc2_i;
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when alu_func_csrr_c => res_o <= csr_i;
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when alu_func_copro_c => res_o <= cp_res;
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when others => res_o <= alu_res; -- undefined
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end case;
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end process alu_function_mux;
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-- **************************************************************************************************************************
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-- Co-Processors
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-- **************************************************************************************************************************
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-- Co-Processor Arbiter -------------------------------------------------------------------
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-- Co-Processor Arbiter -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Interface:
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-- Interface:
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-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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| Line 191... |
Line 214... |
end if;
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end if;
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end if;
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end if;
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end process cp_arbiter;
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end process cp_arbiter;
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-- is co-processor operation? --
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-- is co-processor operation? --
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_copro_c) else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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-- co-processor select / star trigger --
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-- co-processor select / star trigger --
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cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
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cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
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cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
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cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
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| Line 207... |
Line 230... |
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-- co-processor result - only the *actually selected* co-processor may output data != 0 --
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-- co-processor result - only the *actually selected* co-processor may output data != 0 --
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cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
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cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
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-- ALU Logic Core -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_logic_core: process(ctrl_i, rs1_i, opb)
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begin
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case ctrl_i(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) is
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when alu_logic_cmd_movb_c => logic_res <= opb; -- (default)
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when alu_logic_cmd_xor_c => logic_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_logic_cmd_or_c => logic_res <= rs1_i or opb;
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when alu_logic_cmd_and_c => logic_res <= rs1_i and opb;
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when others => logic_res <= opb; -- undefined
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end case;
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end process alu_logic_core;
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, arith_res, logic_res, csr_i, cp_res)
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begin
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case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
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when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
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when alu_func_cmd_logic_c => res_o <= logic_res;
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when alu_func_cmd_csrr_c => res_o <= csr_i;
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when alu_func_cmd_copro_c => res_o <= cp_res;
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when others => res_o <= arith_res; -- undefined
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end case;
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end process alu_function_mux;
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-- **************************************************************************************************************************
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-- Co-Processors
|
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-- **************************************************************************************************************************
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-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
|
-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
|
neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
|
generic map (
|
generic map (
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
