| Line 53... |
Line 53... |
rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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start_i : in std_ulogic; -- trigger operation
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start_i : in std_ulogic; -- trigger operation
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
|
-- result and status --
|
-- result and status --
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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valid_o : out std_ulogic -- data output valid
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valid_o : out std_ulogic -- data output valid
|
);
|
);
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end neorv32_cpu_cp_shifter;
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end neorv32_cpu_cp_shifter;
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|
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architecture neorv32_cpu_cp_shifter_rtl of neorv32_cpu_cp_shifter is
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architecture neorv32_cpu_cp_shifter_rtl of neorv32_cpu_cp_shifter is
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|
|
-- operands --
|
|
signal shift_amount : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0);
|
|
|
|
-- serial shifter --
|
-- serial shifter --
|
type shifter_t is record
|
type shifter_t is record
|
busy : std_ulogic;
|
busy : std_ulogic;
|
busy_ff : std_ulogic;
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busy_ff : std_ulogic;
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done : std_ulogic;
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done : std_ulogic;
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cnt : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0);
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cnt : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
|
|
res : std_ulogic_vector(data_width_c-1 downto 0);
|
end record;
|
end record;
|
signal shifter : shifter_t;
|
signal shifter : shifter_t;
|
|
|
-- barrel shifter --
|
-- barrel shifter --
|
type bs_level_t is array (index_size_f(data_width_c) downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
|
type bs_level_t is array (index_size_f(data_width_c) downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
|
signal bs_level : bs_level_t;
|
signal bs_level : bs_level_t;
|
signal bs_result : std_ulogic_vector(data_width_c-1 downto 0);
|
signal bs_result : std_ulogic_vector(data_width_c-1 downto 0);
|
|
|
begin
|
begin
|
|
|
-- Shift Amount ---------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
shift_amount <= imm_i(index_size_f(data_width_c)-1 downto 0) when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else -- immediate source
|
|
rs2_i(index_size_f(data_width_c)-1 downto 0); -- register source
|
|
|
|
|
|
-- Iterative Shifter Core (small but slow) ------------------------------------------------
|
-- Iterative Shifter Core (small but slow) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
serial_shifter_sync:
|
serial_shifter_sync:
|
if (FAST_SHIFT_EN = false) generate
|
if (FAST_SHIFT_EN = false) generate
|
shifter_unit_sync: process(rstn_i, clk_i)
|
shifter_unit_sync: process(rstn_i, clk_i)
|
| Line 110... |
Line 101... |
shifter.busy <= '0';
|
shifter.busy <= '0';
|
end if;
|
end if;
|
--
|
--
|
if (start_i = '1') then -- trigger new shift
|
if (start_i = '1') then -- trigger new shift
|
shifter.sreg <= rs1_i; -- shift operand
|
shifter.sreg <= rs1_i; -- shift operand
|
shifter.cnt <= shift_amount; -- shift amount
|
shifter.cnt <= shamt_i; -- shift amount
|
elsif (or_reduce_f(shifter.cnt) = '1') then -- running shift (cnt != 0)
|
elsif (or_reduce_f(shifter.cnt) = '1') then -- running shift (cnt != 0)
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
|
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
|
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
|
else -- SRL: shift right logical / SRA: shift right arithmetical
|
else -- SRL: shift right logical / SRA: shift right arithmetical
|
| Line 123... |
Line 114... |
end if;
|
end if;
|
end if;
|
end if;
|
end process shifter_unit_sync;
|
end process shifter_unit_sync;
|
end generate;
|
end generate;
|
|
|
-- shift control --
|
-- shift control/output --
|
serial_shifter_ctrl:
|
serial_shifter_ctrl:
|
if (FAST_SHIFT_EN = false) generate
|
if (FAST_SHIFT_EN = false) generate
|
shifter.done <= not or_reduce_f(shifter.cnt(shifter.cnt'left downto 1));
|
shifter.done <= not or_reduce_f(shifter.cnt(shifter.cnt'left downto 1));
|
valid_o <= shifter.busy and shifter.done;
|
valid_o <= shifter.busy and shifter.done;
|
res_o <= shifter.sreg when (shifter.busy = '0') and (shifter.busy_ff = '1') else (others => '0');
|
res_o <= shifter.sreg when (shifter.busy = '0') and (shifter.busy_ff = '1') else (others => '0');
|
| Line 136... |
Line 127... |
|
|
-- Barrel Shifter Core (fast but large) ---------------------------------------------------
|
-- Barrel Shifter Core (fast but large) ---------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
barrel_shifter_async:
|
barrel_shifter_async:
|
if (FAST_SHIFT_EN = true) generate
|
if (FAST_SHIFT_EN = true) generate
|
shifter_unit_async: process(rs1_i, shift_amount, ctrl_i, bs_level)
|
shifter_unit_async: process(rs1_i, shamt_i, ctrl_i, bs_level)
|
begin
|
begin
|
-- input level: convert left shifts to right shifts --
|
-- input level: convert left shifts to right shifts --
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift?
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift?
|
bs_level(index_size_f(data_width_c)) <= bit_rev_f(rs1_i); -- reverse bit order of input operand
|
bs_level(index_size_f(data_width_c)) <= bit_rev_f(rs1_i); -- reverse bit order of input operand
|
else
|
else
|
bs_level(index_size_f(data_width_c)) <= rs1_i;
|
bs_level(index_size_f(data_width_c)) <= rs1_i;
|
end if;
|
end if;
|
|
|
-- shifter array --
|
-- shifter array --
|
for i in index_size_f(data_width_c)-1 downto 0 loop
|
for i in index_size_f(data_width_c)-1 downto 0 loop
|
if (shift_amount(i) = '1') then
|
if (shamt_i(i) = '1') then
|
bs_level(i)(data_width_c-1 downto data_width_c-(2**i)) <= (others => (bs_level(i+1)(data_width_c-1) and ctrl_i(ctrl_alu_shift_ar_c)));
|
bs_level(i)(data_width_c-1 downto data_width_c-(2**i)) <= (others => (bs_level(i+1)(data_width_c-1) and ctrl_i(ctrl_alu_shift_ar_c)));
|
bs_level(i)((data_width_c-(2**i))-1 downto 0) <= bs_level(i+1)(data_width_c-1 downto 2**i);
|
bs_level(i)((data_width_c-(2**i))-1 downto 0) <= bs_level(i+1)(data_width_c-1 downto 2**i);
|
else
|
else
|
bs_level(i) <= bs_level(i+1);
|
bs_level(i) <= bs_level(i+1);
|
end if;
|
end if;
|
| Line 178... |
Line 169... |
end if;
|
end if;
|
end if;
|
end if;
|
end process shifter_unit_sync;
|
end process shifter_unit_sync;
|
end generate;
|
end generate;
|
|
|
-- shift control --
|
-- shift control/output --
|
barrel_shifter_ctrl:
|
barrel_shifter_ctrl:
|
if (FAST_SHIFT_EN = true) generate
|
if (FAST_SHIFT_EN = true) generate
|
valid_o <= start_i;
|
valid_o <= start_i;
|
end generate;
|
end generate;
|
|
|
