| Line 4... |
Line 4... |
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). #
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-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). #
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-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). #
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-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). #
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-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 110... |
Line 110... |
end component;
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end component;
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|
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-- cache interface --
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-- cache interface --
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type cache_if_t is record
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type cache_if_t is record
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clear : std_ulogic; -- cache clear
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clear : std_ulogic; -- cache clear
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--
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host_addr : std_ulogic_vector(31 downto 0); -- cpu access address
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host_addr : std_ulogic_vector(31 downto 0); -- cpu access address
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host_rdata : std_ulogic_vector(31 downto 0); -- cpu read data
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host_rdata : std_ulogic_vector(31 downto 0); -- cpu read data
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--
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hit : std_ulogic; -- hit access
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hit : std_ulogic; -- hit access
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--
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ctrl_en : std_ulogic; -- control access enable
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ctrl_en : std_ulogic; -- control access enable
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ctrl_addr : std_ulogic_vector(31 downto 0); -- control access address
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ctrl_addr : std_ulogic_vector(31 downto 0); -- control access address
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ctrl_we : std_ulogic; -- control write enable
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ctrl_we : std_ulogic; -- control write enable
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ctrl_wdata : std_ulogic_vector(31 downto 0); -- control write data
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ctrl_wdata : std_ulogic_vector(31 downto 0); -- control write data
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ctrl_tag_we : std_ulogic; -- control tag write enabled
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ctrl_tag_we : std_ulogic; -- control tag write enabled
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| Line 134... |
Line 131... |
type ctrl_t is record
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type ctrl_t is record
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state : ctrl_engine_state_t; -- current state
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state : ctrl_engine_state_t; -- current state
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state_nxt : ctrl_engine_state_t; -- next state
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state_nxt : ctrl_engine_state_t; -- next state
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addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download
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addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download
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addr_reg_nxt : std_ulogic_vector(31 downto 0);
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addr_reg_nxt : std_ulogic_vector(31 downto 0);
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--
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re_buf : std_ulogic; -- read request buffer
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re_buf : std_ulogic; -- read request buffer
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re_buf_nxt : std_ulogic;
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re_buf_nxt : std_ulogic;
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--
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clear_buf : std_ulogic; -- clear request buffer
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clear_buf : std_ulogic; -- clear request buffer
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clear_buf_nxt : std_ulogic;
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clear_buf_nxt : std_ulogic;
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end record;
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end record;
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signal ctrl : ctrl_t;
|
signal ctrl : ctrl_t;
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|
|
| Line 158... |
Line 153... |
assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error;
|
assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error;
|
|
|
|
|
-- Control Engine FSM Sync ----------------------------------------------------------------
|
-- Control Engine FSM Sync ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- registers that REQUIRE a specific reset state --
|
ctrl_engine_fsm_sync: process(rstn_i, clk_i)
|
ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
ctrl.state <= S_CACHE_CLEAR;
|
ctrl.state <= S_CACHE_CLEAR;
|
ctrl.re_buf <= '0';
|
ctrl.re_buf <= '0';
|
ctrl.clear_buf <= '0';
|
ctrl.clear_buf <= '0';
|
|
ctrl.addr_reg <= (others => '-');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
ctrl.state <= ctrl.state_nxt;
|
ctrl.state <= ctrl.state_nxt;
|
ctrl.re_buf <= ctrl.re_buf_nxt;
|
ctrl.re_buf <= ctrl.re_buf_nxt;
|
ctrl.clear_buf <= ctrl.clear_buf_nxt;
|
ctrl.clear_buf <= ctrl.clear_buf_nxt;
|
end if;
|
|
end process ctrl_engine_fsm_sync_rst;
|
|
|
|
-- registers that do not require a specific reset state --
|
|
ctrl_engine_fsm_sync: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
ctrl.addr_reg <= ctrl.addr_reg_nxt;
|
ctrl.addr_reg <= ctrl.addr_reg_nxt;
|
end if;
|
end if;
|
end process ctrl_engine_fsm_sync;
|
end process ctrl_engine_fsm_sync;
|
|
|
|
|
| Line 343... |
Line 331... |
-- # Cache sets are mapped to individual memory components - no multi-dimensional memory arrays #
|
-- # Cache sets are mapped to individual memory components - no multi-dimensional memory arrays #
|
-- # are used as some synthesis tools have problems to map these to actual BRAM primitives. #
|
-- # are used as some synthesis tools have problems to map these to actual BRAM primitives. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
|
-- # permitted provided that the following conditions are met: #
|
-- # #
|
-- # #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| Line 411... |
Line 399... |
architecture neorv32_icache_memory_rtl of neorv32_icache_memory is
|
architecture neorv32_icache_memory_rtl of neorv32_icache_memory is
|
|
|
-- cache layout --
|
-- cache layout --
|
constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words
|
constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words
|
constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS);
|
constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS);
|
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset
|
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additional bits for byte offset
|
constant cache_entries_c : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set)
|
constant cache_entries_c : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set)
|
|
|
-- status flag memory --
|
-- status flag memory --
|
signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
|
signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
|
signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
|
signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0);
|
