| Line 59... |
Line 59... |
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
|
|
-- "response time window" for processor-internal memories and IO devices
|
-- "response time window" for processor-internal memories and IO devices
|
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
|
|
|
-- jtag tap - identifier --
|
|
constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
|
|
constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
|
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural;
|
function index_size_f(input : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
|
function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
|
| Line 81... |
Line 86... |
function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
|
function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050500"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050509"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
|
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
|
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
|
constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
|
|
|
-- Internal Types -------------------------------------------------------------------------
|
-- Internal Types -------------------------------------------------------------------------
|
| Line 104... |
Line 109... |
-- Internal Bootloader ROM --
|
-- Internal Bootloader ROM --
|
constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!
|
constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!
|
constant boot_rom_size_c : natural := 4*1024; -- module's address space in bytes
|
constant boot_rom_size_c : natural := 4*1024; -- module's address space in bytes
|
constant boot_rom_max_size_c : natural := 32*1024; -- max module's address space in bytes, fixed!
|
constant boot_rom_max_size_c : natural := 32*1024; -- max module's address space in bytes, fixed!
|
|
|
|
-- On-Chip Debugger: Debug Module --
|
|
constant dm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800"; -- base address, fixed!
|
|
constant dm_size_c : natural := 4*32*4; -- debug ROM address space in bytes, fixed
|
|
constant dm_code_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800";
|
|
constant dm_pbuf_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880";
|
|
constant dm_data_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900";
|
|
constant dm_sreg_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980";
|
|
|
-- IO: Peripheral Devices ("IO") Area --
|
-- IO: Peripheral Devices ("IO") Area --
|
-- Control register(s) (including the device-enable) should be located at the base address of each device
|
-- Control register(s) (including the device-enable) should be located at the base address of each device
|
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
|
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
|
constant io_size_c : natural := 64*4; -- module's address space in bytes, fixed!
|
constant io_size_c : natural := 64*4; -- module's address space in bytes, fixed!
|
|
|
| Line 217... |
Line 230... |
|
|
-- System Information Memory (SYSINFO) --
|
-- System Information Memory (SYSINFO) --
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address
|
constant sysinfo_size_c : natural := 8*4; -- module's address space in bytes
|
constant sysinfo_size_c : natural := 8*4; -- module's address space in bytes
|
|
|
-- Main Control Bus -----------------------------------------------------------------------
|
-- Main CPU Control Bus -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- register file --
|
-- register file --
|
constant ctrl_rf_in_mux_c : natural := 0; -- input source select lsb (0=MEM, 1=ALU)
|
constant ctrl_rf_in_mux_c : natural := 0; -- input source select lsb (0=MEM, 1=ALU)
|
constant ctrl_rf_rs1_adr0_c : natural := 1; -- source register 1 address bit 0
|
constant ctrl_rf_rs1_adr0_c : natural := 1; -- source register 1 address bit 0
|
constant ctrl_rf_rs1_adr1_c : natural := 2; -- source register 1 address bit 1
|
constant ctrl_rf_rs1_adr1_c : natural := 2; -- source register 1 address bit 1
|
| Line 298... |
Line 311... |
-- CPU status --
|
-- CPU status --
|
constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb
|
constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb
|
constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb
|
constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb
|
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
|
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
|
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution
|
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution
|
|
constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 73; -- control bus size
|
constant ctrl_width_c : natural := 74; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 381... |
Line 395... |
constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- xor
|
constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- xor
|
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
-- system/csr --
|
-- system/csr --
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ...
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
| Line 399... |
Line 413... |
-- system --
|
-- system --
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
|
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- DRET
|
|
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- atomic operations --
|
-- atomic operations --
|
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
|
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
|
| Line 579... |
Line 594... |
constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
|
constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
|
constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
|
constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
|
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
|
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
|
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
|
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
|
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
|
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
|
---- debug mode registers --
|
-- debug mode registers --
|
--constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
|
constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
|
--constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
|
constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
|
--constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
|
constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
|
--constant csr_dsratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
|
constant csr_dscratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
|
--constant csr_dsratch1_c : std_ulogic_vector(11 downto 0) := x"7b3";
|
|
-- machine counters/timers --
|
-- machine counters/timers --
|
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
|
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
|
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
|
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
|
--
|
--
|
constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := x"b03";
|
constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := x"b03";
|
| Line 758... |
Line 772... |
constant alu_func_cmd_shift_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
|
constant alu_func_cmd_shift_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
|
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
|
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
|
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
-- MSB : 1 = async exception (IRQ); 0 = sync exception (eg. ebreak)
|
|
-- MSB-1 : 1 = entry to debug mode; 0 = normal trapping
|
-- RISC-V compliant sync. exceptions --
|
-- RISC-V compliant sync. exceptions --
|
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0: instruction misaligned
|
constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned
|
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1: instruction access fault
|
constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"; -- 0.1: instruction access fault
|
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2: illegal instruction
|
constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"; -- 0.2: illegal instruction
|
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3: breakpoint
|
constant trap_brk_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00011"; -- 0.3: breakpoint
|
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4: load address misaligned
|
constant trap_lma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00100"; -- 0.4: load address misaligned
|
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5: load access fault
|
constant trap_lbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00101"; -- 0.5: load access fault
|
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned
|
constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"; -- 0.6: store address misaligned
|
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault
|
constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"; -- 0.7: store access fault
|
constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode
|
constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"; -- 0.8: environment call from u-mode
|
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
|
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode
|
-- RISC-V compliant interrupts (async. exceptions) --
|
-- RISC-V compliant interrupts (async. exceptions) --
|
constant trap_nmi_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: non-maskable interrupt
|
constant trap_nmi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00000"; -- 1.0: non-maskable interrupt
|
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt
|
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt
|
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt
|
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt
|
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
|
constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"; -- 1.11: machine external interrupt
|
-- NEORV32-specific (custom) interrupts (async. exceptions) --
|
-- NEORV32-specific (custom) interrupts (async. exceptions) --
|
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
|
constant trap_firq3_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10011"; -- 1.19: fast interrupt 3
|
constant trap_firq4_c : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
|
constant trap_firq4_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10100"; -- 1.20: fast interrupt 4
|
constant trap_firq5_c : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
|
constant trap_firq5_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10101"; -- 1.21: fast interrupt 5
|
constant trap_firq6_c : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
|
constant trap_firq6_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10110"; -- 1.22: fast interrupt 6
|
constant trap_firq7_c : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
|
constant trap_firq7_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10111"; -- 1.23: fast interrupt 7
|
constant trap_firq8_c : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
|
constant trap_firq8_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11000"; -- 1.24: fast interrupt 8
|
constant trap_firq9_c : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
|
constant trap_firq9_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11001"; -- 1.25: fast interrupt 9
|
constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
|
constant trap_firq10_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11010"; -- 1.26: fast interrupt 10
|
constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
|
constant trap_firq11_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11011"; -- 1.27: fast interrupt 11
|
constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
|
constant trap_firq12_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11100"; -- 1.28: fast interrupt 12
|
constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
|
constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"; -- 1.29: fast interrupt 13
|
constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
|
constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14
|
constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
|
constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15
|
|
-- entering debug mode - cause --
|
|
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- break instruction (sync / EXCEPTION)
|
|
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async / IRQ)
|
|
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async / IRQ)
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iaccess_c : natural := 0; -- instruction access fault
|
constant exception_iillegal_c : natural := 1; -- illegal instrution
|
constant exception_iillegal_c : natural := 1; -- illegal instruction
|
constant exception_ialign_c : natural := 2; -- instrution address misaligned
|
constant exception_ialign_c : natural := 2; -- instruction address misaligned
|
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
|
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
|
constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode
|
constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode
|
constant exception_break_c : natural := 5; -- breakpoint
|
constant exception_break_c : natural := 5; -- breakpoint
|
constant exception_salign_c : natural := 6; -- store address misaligned
|
constant exception_salign_c : natural := 6; -- store address misaligned
|
constant exception_lalign_c : natural := 7; -- load address misaligned
|
constant exception_lalign_c : natural := 7; -- load address misaligned
|
constant exception_saccess_c : natural := 8; -- store access fault
|
constant exception_saccess_c : natural := 8; -- store access fault
|
constant exception_laccess_c : natural := 9; -- load access fault
|
constant exception_laccess_c : natural := 9; -- load access fault
|
|
-- for debug mode only --
|
|
constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
|
--
|
--
|
constant exception_width_c : natural := 10; -- length of this list in bits
|
constant exception_width_c : natural := 11; -- length of this list in bits
|
-- interrupt source bits --
|
-- interrupt source bits --
|
constant interrupt_nm_irq_c : natural := 0; -- non-maskable interrupt
|
constant interrupt_nm_irq_c : natural := 0; -- non-maskable interrupt
|
constant interrupt_msw_irq_c : natural := 1; -- machine software interrupt
|
constant interrupt_msw_irq_c : natural := 1; -- machine software interrupt
|
constant interrupt_mtime_irq_c : natural := 2; -- machine timer interrupt
|
constant interrupt_mtime_irq_c : natural := 2; -- machine timer interrupt
|
constant interrupt_mext_irq_c : natural := 3; -- machine external interrupt
|
constant interrupt_mext_irq_c : natural := 3; -- machine external interrupt
|
| Line 828... |
Line 850... |
constant interrupt_firq_11_c : natural := 15; -- fast interrupt channel 11
|
constant interrupt_firq_11_c : natural := 15; -- fast interrupt channel 11
|
constant interrupt_firq_12_c : natural := 16; -- fast interrupt channel 12
|
constant interrupt_firq_12_c : natural := 16; -- fast interrupt channel 12
|
constant interrupt_firq_13_c : natural := 17; -- fast interrupt channel 13
|
constant interrupt_firq_13_c : natural := 17; -- fast interrupt channel 13
|
constant interrupt_firq_14_c : natural := 18; -- fast interrupt channel 14
|
constant interrupt_firq_14_c : natural := 18; -- fast interrupt channel 14
|
constant interrupt_firq_15_c : natural := 19; -- fast interrupt channel 15
|
constant interrupt_firq_15_c : natural := 19; -- fast interrupt channel 15
|
|
-- for debug mode only --
|
|
constant interrupt_db_halt_c : natural := 20; -- enter debug mode via external halt request ("async IRQ")
|
|
constant interrupt_db_step_c : natural := 21; -- enter debug mode via single-stepping ("async IRQ")
|
--
|
--
|
constant interrupt_width_c : natural := 20; -- length of this list in bits
|
constant interrupt_width_c : natural := 22; -- length of this list in bits
|
|
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
| Line 876... |
Line 901... |
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
|
-- On-Chip Debugger (OCD) --
|
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
| Line 933... |
Line 960... |
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
-- JTAG on-chip debugger interface --
|
|
jtag_trst_i : in std_ulogic := '0'; -- low-active TAP reset (optional)
|
|
jtag_tck_i : in std_ulogic := '0'; -- serial clock
|
|
jtag_tdi_i : in std_ulogic := '0'; -- serial data input
|
|
jtag_tdo_o : out std_ulogic; -- serial data output
|
|
jtag_tms_i : in std_ulogic := '0'; -- mode select
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
| Line 978... |
Line 1011... |
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
-- NCO output (available if IO_NCO_EN = true) --
|
-- NCO output (available if IO_NCO_EN = true) --
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
neoled_o : out std_ulogic; -- async serial data line
|
neoled_o : out std_ulogic; -- async serial data line
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
-- System time --
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
|
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
-- Interrupts --
|
-- Interrupts --
|
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
|
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
|
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
|
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
| Line 996... |
Line 1030... |
component neorv32_cpu
|
component neorv32_cpu
|
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
|
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
TINY_SHIFT_EN : boolean := false; -- use tiny (single-bit) shifter for shift operations
|
TINY_SHIFT_EN : boolean := false; -- use tiny (single-bit) shifter for shift operations
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
| Line 1057... |
Line 1093... |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
|
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
|
firq_ack_o : out std_ulogic_vector(15 downto 0)
|
firq_ack_o : out std_ulogic_vector(15 downto 0);
|
|
-- debug mode (halt) request --
|
|
db_halt_req_i : in std_ulogic := '0'
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_control
|
component neorv32_cpu_control
|
generic (
|
generic (
|
-- General --
|
-- General --
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
| Line 1110... |
Line 1150... |
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- FPU interface --
|
-- FPU interface --
|
fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
|
fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
|
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
|
fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
|
|
-- debug mode (halt) request --
|
|
db_halt_req_i : in std_ulogic;
|
-- non-maskable interrupt --
|
-- non-maskable interrupt --
|
nm_irq_i : in std_ulogic;
|
nm_irq_i : in std_ulogic;
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
| Line 1312... |
Line 1354... |
|
|
-- Component: Bus Keeper ------------------------------------------------------------------
|
-- Component: Bus Keeper ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_bus_keeper is
|
component neorv32_bus_keeper is
|
generic (
|
generic (
|
|
-- External memory interface --
|
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
|
| Line 1795... |
Line 1839... |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2
|
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
|
-- On-Chip Debugger --
|
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement OCD?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
| Line 1819... |
Line 1865... |
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Component: On-Chip Debugger - Debug Module (DM) ----------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_debug_dm
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
|
-- debug module interface (DMI) --
|
|
dmi_rstn_i : in std_ulogic;
|
|
dmi_req_valid_i : in std_ulogic;
|
|
dmi_req_ready_o : out std_ulogic; -- DMI is allowed to make new requests when set
|
|
dmi_req_addr_i : in std_ulogic_vector(06 downto 0);
|
|
dmi_req_op_i : in std_ulogic; -- 0=read, 1=write
|
|
dmi_req_data_i : in std_ulogic_vector(31 downto 0);
|
|
dmi_resp_valid_o : out std_ulogic; -- response valid when set
|
|
dmi_resp_ready_i : in std_ulogic; -- ready to receive respond
|
|
dmi_resp_data_o : out std_ulogic_vector(31 downto 0);
|
|
dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error
|
|
-- CPU bus access --
|
|
cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
cpu_rden_i : in std_ulogic; -- read enable
|
|
cpu_wren_i : in std_ulogic; -- write enable
|
|
cpu_data_i : in std_ulogic_vector(31 downto 0); -- data in
|
|
cpu_data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
cpu_ack_o : out std_ulogic; -- transfer acknowledge
|
|
-- CPU control --
|
|
cpu_ndmrstn_o : out std_ulogic; -- soc reset
|
|
cpu_halt_req_o : out std_ulogic -- request hart to halt (enter debug mode)
|
|
);
|
|
end component;
|
|
|
|
-- Component: On-Chip Debugger - Debug Transport Module (DTM) -----------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_debug_dtm
|
|
generic (
|
|
IDCODE_VERSION : std_ulogic_vector(03 downto 0) := x"0"; -- version
|
|
IDCODE_PARTID : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
|
|
IDCODE_MANID : std_ulogic_vector(10 downto 0) := "00000000000" -- manufacturer id
|
|
);
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
|
-- jtag connection --
|
|
jtag_trst_i : in std_ulogic;
|
|
jtag_tck_i : in std_ulogic;
|
|
jtag_tdi_i : in std_ulogic;
|
|
jtag_tdo_o : out std_ulogic;
|
|
jtag_tms_i : in std_ulogic;
|
|
-- debug module interface (DMI) --
|
|
dmi_rstn_o : out std_ulogic;
|
|
dmi_req_valid_o : out std_ulogic;
|
|
dmi_req_ready_i : in std_ulogic; -- DMI is allowed to make new requests when set
|
|
dmi_req_addr_o : out std_ulogic_vector(06 downto 0);
|
|
dmi_req_op_o : out std_ulogic; -- 0=read, 1=write
|
|
dmi_req_data_o : out std_ulogic_vector(31 downto 0);
|
|
dmi_resp_valid_i : in std_ulogic; -- response valid when set
|
|
dmi_resp_ready_o : out std_ulogic; -- ready to receive respond
|
|
dmi_resp_data_i : in std_ulogic_vector(31 downto 0);
|
|
dmi_resp_err_i : in std_ulogic -- 0=ok, 1=error
|
|
);
|
|
end component;
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
package body neorv32_package is
|
package body neorv32_package is
|
|
|
-- Function: Minimal required number of bits to represent input number --------------------
|
-- Function: Minimal required number of bits to represent input number --------------------
|
