| Line 43... |
Line 43... |
-- address space --
|
-- address space --
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
|
-- CPU core --
|
-- CPU core --
|
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
|
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
|
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
|
|
|
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
| Line 62... |
Line 62... |
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060202"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060300"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- External Interface Types ---------------------------------------------------------------
|
-- External Interface Types ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
| Line 215... |
Line 215... |
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70"; -- base address
|
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70"; -- base address
|
--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes
|
--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes
|
|
|
-- reserved --
|
-- reserved --
|
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78"; -- base address
|
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78"; -- base address
|
--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes
|
--constant reserved_size_c : natural := 1*4; -- module's address space size in bytes
|
|
|
|
-- Bus Access Monitor (BUSKEEPER) --
|
|
constant buskeeper_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff7c"; -- base address
|
|
constant buskeeper_size_c : natural := 1*4; -- module's address space size in bytes
|
|
|
-- External Interrupt Controller (XIRQ) --
|
-- External Interrupt Controller (XIRQ) --
|
constant xirq_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
|
constant xirq_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
|
constant xirq_size_c : natural := 4*4; -- module's address space size in bytes
|
constant xirq_size_c : natural := 4*4; -- module's address space size in bytes
|
constant xirq_enable_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
|
constant xirq_enable_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
|
| Line 421... |
Line 425... |
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
-- atomic memory access (A) --
|
-- atomic memory access (A) --
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction
|
|
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- control flow --
|
-- control flow --
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
| Line 460... |
Line 464... |
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
-- fence --
|
-- fence --
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync
|
|
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- system --
|
-- system --
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
| Line 897... |
Line 901... |
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
-- On-Chip Debugger (OCD) --
|
-- On-Chip Debugger (OCD) --
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zbb : boolean := false; -- implement basic bit-manipulation sub-extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
|
|
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
| Line 1047... |
Line 1053... |
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
|
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
| Line 1121... |
Line 1129... |
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
|
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
| Line 1211... |
Line 1221... |
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_alu
|
component neorv32_cpu_alu
|
generic (
|
generic (
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
|
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
|
| Line 1254... |
Line 1264... |
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
start_i : in std_ulogic; -- trigger operation
|
start_i : in std_ulogic; -- trigger operation
|
-- data input --
|
-- data input --
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
|
-- result and status --
|
-- result and status --
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
);
|
);
|
end component;
|
end component;
|
| Line 1300... |
Line 1309... |
start_i : in std_ulogic; -- trigger operation
|
start_i : in std_ulogic; -- trigger operation
|
-- data input --
|
-- data input --
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
|
shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount
|
-- result and status --
|
-- result and status --
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
);
|
);
|
end component;
|
end component;
|
| Line 1404... |
Line 1414... |
MEM_INT_DMEM_SIZE : natural -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural -- size of processor-internal data memory in bytes
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ack_i : in std_ulogic; -- transfer acknowledge from bus system
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
err_i : in std_ulogic; -- transfer error from bus system
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic -- bus error
|
err_o : out std_ulogic; -- transfer error
|
|
-- bus monitoring --
|
|
bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
bus_rden_i : in std_ulogic; -- read enable
|
|
bus_wren_i : in std_ulogic; -- write enable
|
|
bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
|
|
bus_err_i : in std_ulogic -- transfer error from bus system
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1901... |
Line 1917... |
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS : natural; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural; -- number of regions (0..64)
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory --
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-- Internal Data memory --
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MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
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