| Line 42... |
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- address space --
|
-- address space --
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
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constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
|
|
|
-- CPU core --
|
-- use dedicated hardware reset value for UNCRITICAL registers --
|
constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
|
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
|
|
constant dedicated_reset_c : boolean := false;
|
|
|
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
|
|
-- "response time window" for processor-internal modules --
|
-- "response time window" for processor-internal modules --
|
constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
-- = cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
|
constant max_proc_int_response_time_c : natural := 15;
|
|
|
-- jtag tap - identifier --
|
-- jtag tap - identifier --
|
constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
|
constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
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constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
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constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
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constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060700"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060800"; -- no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
| Line 406... |
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-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
|
|
-- RISC-V Opcode Layout -------------------------------------------------------------------
|
-- RISC-V 32-Bit Instruction Word Layout --------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
|
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
|
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
|
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
|
constant instr_rd_lsb_c : natural := 7; -- destination register address bit 0
|
constant instr_rd_lsb_c : natural := 7; -- destination register address bit 0
|
constant instr_rd_msb_c : natural := 11; -- destination register address bit 4
|
constant instr_rd_msb_c : natural := 11; -- destination register address bit 4
|
| Line 452... |
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constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
-- atomic memory access (A) --
|
-- atomic memory access (A) --
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction
|
|
-- official "custom0/1" RISC-V opcodes - free for custom instructions --
|
|
constant opcode_cust0_c : std_ulogic_vector(6 downto 0) := "0001011"; -- custom instructions 0
|
|
--constant opcode_cust1_c : std_ulogic_vector(6 downto 0) := "0101011"; -- custom instructions 1
|
|
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- control flow --
|
-- control flow --
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
| Line 482... |
Line 487... |
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
-- system/csr --
|
-- system/csr --
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ...
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ...
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- csr r/w
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- csr read & set bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- csr read & clear bit
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- csr r/w immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- csr read & set bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- csr read & clear bit immediate
|
-- fence --
|
-- fence --
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync
|
|
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- system --
|
-- system --
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ecall
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- ebreak
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- mret
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- wfi
|
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- DRET
|
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- dret
|
|
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- atomic operations --
|
-- atomic operations --
|
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
|
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- lr.w
|
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
|
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- sc.w
|
|
|
-- RISC-V Floating-Point Stuff ------------------------------------------------------------
|
-- RISC-V Floating-Point Stuff ------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- formats --
|
-- formats --
|
constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
|
constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
|
constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
|
--constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
|
constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
|
--constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
|
constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
|
--constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
|
|
|
-- number class flags --
|
-- number class flags --
|
constant fp_class_neg_inf_c : natural := 0; -- negative infinity
|
constant fp_class_neg_inf_c : natural := 0; -- negative infinity
|
constant fp_class_neg_norm_c : natural := 1; -- negative normal number
|
constant fp_class_neg_norm_c : natural := 1; -- negative normal number
|
constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number
|
constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number
|
| Line 685... |
Line 690... |
constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
|
constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
|
constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
|
constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
|
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
|
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
|
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
|
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
|
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
|
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
|
|
-- trigger module registers --
|
|
constant csr_class_trigger_c : std_ulogic_vector(07 downto 0) := x"7a"; -- trigger registers
|
|
constant csr_tselect_c : std_ulogic_vector(11 downto 0) := x"7a0";
|
|
constant csr_tdata1_c : std_ulogic_vector(11 downto 0) := x"7a1";
|
|
constant csr_tdata2_c : std_ulogic_vector(11 downto 0) := x"7a2";
|
|
constant csr_tdata3_c : std_ulogic_vector(11 downto 0) := x"7a3";
|
|
constant csr_tinfo_c : std_ulogic_vector(11 downto 0) := x"7a4";
|
|
constant csr_tcontrol_c : std_ulogic_vector(11 downto 0) := x"7a5";
|
|
constant csr_mcontext_c : std_ulogic_vector(11 downto 0) := x"7a8";
|
|
constant csr_scontext_c : std_ulogic_vector(11 downto 0) := x"7aa";
|
-- debug mode registers --
|
-- debug mode registers --
|
constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
|
constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
|
constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
|
constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
|
constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
|
constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
|
constant csr_dscratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
|
constant csr_dscratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
|
| Line 772... |
Line 787... |
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
|
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
|
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
|
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
|
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15";
|
constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15";
|
|
|
-- Co-Processor IDs -----------------------------------------------------------------------
|
-- <<< NEORV32-specific (custom) read-only CSRs >>> ---
|
|
-- machine extended ISA extensionss information --
|
|
constant csr_mxisa_c : std_ulogic_vector(11 downto 0) := x"fc0";
|
|
|
|
-- CPU Co-Processor IDs -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA)
|
constant cp_sel_shifter_c : std_ulogic_vector(2 downto 0) := "000"; -- CP0: shift operations (base ISA)
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions)
|
constant cp_sel_muldiv_c : std_ulogic_vector(2 downto 0) := "001"; -- CP1: multiplication/division operations ('M' extensions)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions)
|
constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- CP2: bit manipulation ('B' extensions)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension)
|
constant cp_sel_fpu_c : std_ulogic_vector(2 downto 0) := "011"; -- CP3: floating-point unit ('Zfinx' extension)
|
--constant cp_sel_res0_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: reserved
|
constant cp_sel_cfu_c : std_ulogic_vector(2 downto 0) := "100"; -- CP4: custom instructions CFU ('Zxcfu' extension)
|
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved
|
--constant cp_sel_res1_c : std_ulogic_vector(2 downto 0) := "101"; -- CP5: reserved
|
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved
|
--constant cp_sel_res2_c : std_ulogic_vector(2 downto 0) := "110"; -- CP6: reserved
|
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved
|
--constant cp_sel_res3_c : std_ulogic_vector(2 downto 0) := "111"; -- CP7: reserved
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes ---------------------------------------------------------------------
|
| Line 804... |
Line 823... |
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- Trap ID Codes --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
|
-- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak)
|
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
|
-- MSB-1: 1 = entry to debug mode, 0 = normal trapping
|
-- RISC-V compliant sync. exceptions --
|
-- RISC-V compliant synchronous exceptions --
|
constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned
|
constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned
|
constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"; -- 0.1: instruction access fault
|
constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"; -- 0.1: instruction access fault
|
constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"; -- 0.2: illegal instruction
|
constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"; -- 0.2: illegal instruction
|
constant trap_brk_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00011"; -- 0.3: breakpoint
|
constant trap_brk_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00011"; -- 0.3: breakpoint
|
constant trap_lma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00100"; -- 0.4: load address misaligned
|
constant trap_lma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00100"; -- 0.4: load address misaligned
|
constant trap_lbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00101"; -- 0.5: load access fault
|
constant trap_lbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00101"; -- 0.5: load access fault
|
constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"; -- 0.6: store address misaligned
|
constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"; -- 0.6: store address misaligned
|
constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"; -- 0.7: store access fault
|
constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"; -- 0.7: store access fault
|
constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"; -- 0.8: environment call from u-mode
|
constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"; -- 0.8: environment call from u-mode
|
|
--constant trap_senv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01001"; -- 0.9: environment call from s-mode
|
|
--constant trap_henv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01010"; -- 0.10: environment call from h-mode
|
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode
|
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode
|
-- RISC-V compliant interrupts (async. exceptions) --
|
--constant trap_ipf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01100"; -- 0.12: instruction page fault
|
|
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01101"; -- 0.13: load page fault
|
|
--constant trap_???_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01110"; -- 0.14: reserved
|
|
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01111"; -- 0.15: store page fault
|
|
-- NEORV32-specific (custom) synchronous exceptions --
|
|
-- none implemented yet
|
|
-- RISC-V compliant asynchronous exceptions (interrupts) --
|
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt
|
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt
|
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt
|
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt
|
constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"; -- 1.11: machine external interrupt
|
constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"; -- 1.11: machine external interrupt
|
-- NEORV32-specific (custom) interrupts (async. exceptions) --
|
-- NEORV32-specific (custom) asynchronous exceptions (interrupts) --
|
constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq3_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10011"; -- 1.19: fast interrupt 3
|
constant trap_firq3_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10011"; -- 1.19: fast interrupt 3
|
constant trap_firq4_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10100"; -- 1.20: fast interrupt 4
|
constant trap_firq4_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10100"; -- 1.20: fast interrupt 4
|
| Line 836... |
Line 863... |
constant trap_firq11_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11011"; -- 1.27: fast interrupt 11
|
constant trap_firq11_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11011"; -- 1.27: fast interrupt 11
|
constant trap_firq12_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11100"; -- 1.28: fast interrupt 12
|
constant trap_firq12_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11100"; -- 1.28: fast interrupt 12
|
constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"; -- 1.29: fast interrupt 13
|
constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"; -- 1.29: fast interrupt 13
|
constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14
|
constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14
|
constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15
|
constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15
|
-- entering debug mode - cause --
|
-- entering debug mode (sync./async. exceptions) --
|
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- break instruction (sync / EXCEPTION)
|
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00001"; -- break instruction (sync)
|
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async / IRQ)
|
constant trap_db_hw_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- hardware trigger (sync)
|
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async / IRQ)
|
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async)
|
|
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async)
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instruction access fault
|
constant exception_iaccess_c : natural := 0; -- instruction access fault
|
| Line 856... |
Line 884... |
constant exception_lalign_c : natural := 7; -- load address misaligned
|
constant exception_lalign_c : natural := 7; -- load address misaligned
|
constant exception_saccess_c : natural := 8; -- store access fault
|
constant exception_saccess_c : natural := 8; -- store access fault
|
constant exception_laccess_c : natural := 9; -- load access fault
|
constant exception_laccess_c : natural := 9; -- load access fault
|
-- for debug mode only --
|
-- for debug mode only --
|
constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
|
constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
|
|
constant exception_db_hw_c : natural := 11; -- enter debug mode via hw trigger ("sync EXCEPTION")
|
--
|
--
|
constant exception_width_c : natural := 11; -- length of this list in bits
|
constant exception_width_c : natural := 12; -- length of this list in bits
|
-- interrupt source bits --
|
-- interrupt source bits --
|
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
|
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
|
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
|
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
|
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
|
| Line 909... |
Line 938... |
constant hpmcnt_event_trap_c : natural := 13; -- Entered trap
|
constant hpmcnt_event_trap_c : natural := 13; -- Entered trap
|
constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
|
constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
|
--
|
--
|
constant hpmcnt_event_size_c : natural := 15; -- length of this list
|
constant hpmcnt_event_size_c : natural := 15; -- length of this list
|
|
|
-- Clock Generator ------------------------------------------------------------------------
|
-- SoC Clock Generator --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant clk_div2_c : natural := 0;
|
constant clk_div2_c : natural := 0;
|
constant clk_div4_c : natural := 1;
|
constant clk_div4_c : natural := 1;
|
constant clk_div8_c : natural := 2;
|
constant clk_div8_c : natural := 2;
|
constant clk_div64_c : natural := 3;
|
constant clk_div64_c : natural := 3;
|
| Line 943... |
Line 972... |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
-- Extension Options --
|
CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
|
|
-- Tuning Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
| Line 1060... |
Line 1090... |
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI (available if IO_TWI_EN = true) --
|
-- TWI (available if IO_TWI_EN = true) --
|
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels
|
-- Custom Functions Subsystem IO --
|
-- Custom Functions Subsystem IO --
|
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
|
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
|
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
| Line 1102... |
Line 1132... |
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Tuning Options --
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
| Line 1179... |
Line 1210... |
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
| Line 1265... |
Line 1299... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
|
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
|
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
|
);
|
);
|
port (
|
port (
|
| Line 1377... |
Line 1412... |
fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
|
fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Component: CPU Co-Processor Custom (Instr.) Functions Unit ('Zxcfu' extension) ---------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_cpu_cp_cfu
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
|
start_i : in std_ulogic; -- trigger operation
|
|
-- data input --
|
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
|
-- result and status --
|
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
|
valid_o : out std_ulogic -- data output valid
|
|
);
|
|
end component;
|
|
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
| Line 1572... |
Line 1625... |
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
err_o : out std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1604... |
Line 1658... |
BOOTROM_BASE : std_ulogic_vector(31 downto 0) -- boot ROM base address
|
BOOTROM_BASE : std_ulogic_vector(31 downto 0) -- boot ROM base address
|
);
|
);
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
|
wren_i : in std_ulogic; -- write enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
err_o : out std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Machine System Timer (mtime) ------------------------------------------------
|
-- Component: Machine System Timer (mtime) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 2017... |
Line 2073... |
component neorv32_sysinfo
|
component neorv32_sysinfo
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
-- RISC-V CPU Extensions --
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
|
|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
|
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
|
-- Extension Options --
|
|
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
|
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
|
|
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
|
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural; -- number of regions (0..64)
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
|
