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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_pwm.vhd] - Diff between revs 66 and 70
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| Rev 66 |
Rev 70 |
| Line 57... |
Line 57... |
ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- pwm output channels --
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-- pwm output channels --
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pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0)
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pwm_o : out std_ulogic_vector(59 downto 0)
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);
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);
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end neorv32_pwm;
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end neorv32_pwm;
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architecture neorv32_pwm_rtl of neorv32_pwm is
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architecture neorv32_pwm_rtl of neorv32_pwm is
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| Line 184... |
Line 184... |
elsif (prsc_tick = '1') then
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elsif (prsc_tick = '1') then
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pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
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pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
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end if;
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end if;
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-- channels --
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-- channels --
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pwm_o <= (others => '0');
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for i in 0 to NUM_CHANNELS-1 loop
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for i in 0 to NUM_CHANNELS-1 loop
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if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then
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if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then
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pwm_o(i) <= '0';
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pwm_o(i) <= '0';
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else
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else
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pwm_o(i) <= '1';
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pwm_o(i) <= '1';
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