| Line 3... |
Line 3... |
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project #
|
-- # This is the top entity of the NEORV32 PROCESSOR. Instantiate this unit in your own project #
|
-- # and define all the configuration generics according to your needs. Alternatively, you can use #
|
-- # and define all the configuration generics according to your needs. Alternatively, you can use #
|
-- # one of the alternative top entities provided in the "rtl/top_templates" folder. #
|
-- # one of the alternative top entities provided in the "rtl/top_templates" folder. #
|
-- # #
|
-- # #
|
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
|
-- # Check out the processor's documentation for more information. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
| Line 51... |
Line 51... |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_EN : boolean := true; -- implement processor-internal bootloader?
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
|
|
|
-- On-Chip Debugger (OCD) --
|
|
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
|
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
| Line 117... |
Line 120... |
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
|
|
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
|
|
jtag_trst_i : in std_ulogic := '0'; -- low-active TAP reset (optional)
|
|
jtag_tck_i : in std_ulogic := '0'; -- serial clock
|
|
jtag_tdi_i : in std_ulogic := '0'; -- serial data input
|
|
jtag_tdo_o : out std_ulogic; -- serial data output
|
|
jtag_tms_i : in std_ulogic := '0'; -- mode select
|
|
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
| Line 173... |
Line 183... |
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
|
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
neoled_o : out std_ulogic; -- async serial data line
|
neoled_o : out std_ulogic; -- async serial data line
|
|
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
-- System time --
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
|
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
|
|
-- Interrupts --
|
-- Interrupts --
|
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
|
nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
|
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
|
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
| Line 236... |
Line 247... |
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
lock : std_ulogic; -- exclusive access request
|
lock : std_ulogic; -- exclusive access request
|
end record;
|
end record;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
|
|
|
-- debug core interface (DCI) --
|
|
signal dci_ndmrstn : std_ulogic;
|
|
signal dci_halt_req : std_ulogic;
|
|
|
|
-- debug module interface (DMI) --
|
|
type dmi_t is record
|
|
rstn : std_ulogic;
|
|
req_valid : std_ulogic;
|
|
req_ready : std_ulogic; -- DMI is allowed to make new requests when set
|
|
req_addr : std_ulogic_vector(06 downto 0);
|
|
req_op : std_ulogic; -- 0=read, 1=write
|
|
req_data : std_ulogic_vector(31 downto 0);
|
|
resp_valid : std_ulogic; -- response valid when set
|
|
resp_ready : std_ulogic; -- ready to receive respond
|
|
resp_data : std_ulogic_vector(31 downto 0);
|
|
resp_err : std_ulogic; -- 0=ok, 1=error
|
|
end record;
|
|
signal dmi : dmi_t;
|
|
|
-- io space access --
|
-- io space access --
|
signal io_acc : std_ulogic;
|
signal io_acc : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_wren : std_ulogic;
|
signal io_wren : std_ulogic;
|
|
|
-- read-back busses -
|
-- read-back buses -
|
signal imem_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal imem_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal imem_ack : std_ulogic;
|
signal imem_ack : std_ulogic;
|
signal dmem_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal dmem_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal dmem_ack : std_ulogic;
|
signal dmem_ack : std_ulogic;
|
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
| Line 278... |
Line 308... |
signal neoled_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal neoled_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal neoled_ack : std_ulogic;
|
signal neoled_ack : std_ulogic;
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_ack : std_ulogic;
|
signal sysinfo_ack : std_ulogic;
|
signal bus_keeper_err : std_ulogic;
|
signal bus_keeper_err : std_ulogic;
|
|
signal dm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
|
signal dm_ack : std_ulogic;
|
|
|
-- IRQs --
|
-- IRQs --
|
signal mtime_irq : std_ulogic;
|
signal mtime_irq : std_ulogic;
|
--
|
--
|
signal fast_irq : std_ulogic_vector(15 downto 0);
|
signal fast_irq : std_ulogic_vector(15 downto 0);
|
| Line 326... |
Line 358... |
-- memory system - layout warning --
|
-- memory system - layout warning --
|
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning;
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning;
|
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only --
|
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note;
|
|
-- on-chip debugger --
|
|
assert not (ON_CHIP_DEBUGGER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing on-chip debugger (OCD)." severity note;
|
|
|
|
|
-- Reset Generator ------------------------------------------------------------------------
|
-- Reset Generator ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
reset_generator_sync: process(clk_i)
|
reset_generator_sync: process(clk_i)
|
begin
|
begin
|
| Line 350... |
Line 385... |
rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
|
rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
|
end if;
|
end if;
|
end process reset_generator;
|
end process reset_generator;
|
|
|
ext_rstn <= rstn_gen(rstn_gen'left); -- the beautified external reset signal
|
ext_rstn <= rstn_gen(rstn_gen'left); -- the beautified external reset signal
|
sys_rstn <= ext_rstn and wdt_rstn; -- system reset - can also be triggered by watchdog
|
|
|
-- internal reset buffer --
|
|
soc_reset_generator: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn; -- system reset: can also be triggered by watchdog and debug module
|
|
end if;
|
|
end process soc_reset_generator;
|
|
|
|
|
-- Clock Generator ------------------------------------------------------------------------
|
-- Clock Generator ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
clock_generator: process(sys_rstn, clk_i)
|
clock_generator: process(sys_rstn, clk_i)
|
| Line 402... |
Line 444... |
neorv32_cpu_inst: neorv32_cpu
|
neorv32_cpu_inst: neorv32_cpu
|
generic map (
|
generic map (
|
-- General --
|
-- General --
|
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address
|
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address
|
|
CPU_DEBUG_ADDR => dm_base_c, -- cpu debug mode start address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
| Line 462... |
Line 506... |
msw_irq_i => msw_irq_i, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_ack_o => fast_irq_ack -- fast interrupt acknowledge mask
|
firq_ack_o => fast_irq_ack, -- fast interrupt acknowledge mask
|
|
-- debug mode (halt) request --
|
|
db_halt_req_i => dci_halt_req
|
);
|
);
|
|
|
-- misc --
|
-- misc --
|
cpu_i.src <= '1'; -- initialized but unused
|
cpu_i.src <= '1'; -- initialized but unused
|
cpu_d.src <= '0'; -- initialized but unused
|
cpu_d.src <= '0'; -- initialized but unused
|
| Line 603... |
Line 649... |
-- static signals --
|
-- static signals --
|
p_bus.priv <= cpu_i.priv; -- current CPU privilege level: cpu_i.priv == cpu_d.priv
|
p_bus.priv <= cpu_i.priv; -- current CPU privilege level: cpu_i.priv == cpu_d.priv
|
|
|
-- processor bus: CPU transfer data input --
|
-- processor bus: CPU transfer data input --
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or neoled_rdata or sysinfo_rdata);
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or neoled_rdata or sysinfo_rdata) or dm_rdata;
|
|
|
-- processor bus: CPU transfer ACK input --
|
-- processor bus: CPU transfer ACK input --
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart0_ack or uart1_ack or
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack);
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack) or dm_ack;
|
|
|
-- processor bus: CPU transfer data bus error input --
|
-- processor bus: CPU transfer data bus error input --
|
p_bus.err <= bus_keeper_err or wishbone_err;
|
p_bus.err <= bus_keeper_err or wishbone_err;
|
|
|
|
|
-- Processor-Internal Bus Keeper (BUSKEEPER) ----------------------------------------------
|
-- Processor-Internal Bus Keeper (BUS_KEEPER) ---------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_bus_keeper_inst: neorv32_bus_keeper
|
neorv32_bus_keeper_inst: neorv32_bus_keeper
|
generic map (
|
generic map (
|
|
-- External memory interface --
|
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
| Line 930... |
Line 978... |
mtime_time <= mtime_i; -- use external machine timer time signal
|
mtime_time <= mtime_i; -- use external machine timer time signal
|
mtime_ack <= '0';
|
mtime_ack <= '0';
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
end generate;
|
end generate;
|
|
|
|
mtime_o <= mtime_time when (IO_MTIME_EN = true) else (others => '0'); -- system time output
|
|
|
|
|
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
|
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_uart0_inst_true:
|
neorv32_uart0_inst_true:
|
if (IO_UART0_EN = true) generate
|
if (IO_UART0_EN = true) generate
|
| Line 1236... |
Line 1286... |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
|
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
|
-- On-Chip Debugger --
|
|
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
| Line 1260... |
Line 1312... |
data_o => sysinfo_rdata, -- data out
|
data_o => sysinfo_rdata, -- data out
|
ack_o => sysinfo_ack -- transfer acknowledge
|
ack_o => sysinfo_ack -- transfer acknowledge
|
);
|
);
|
|
|
|
|
|
-- **************************************************************************************************************************
|
|
-- On-Chip Debugger Complex
|
|
-- **************************************************************************************************************************
|
|
|
|
|
|
-- On-Chip Debugger - Debug Module (DM) ---------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_neorv32_debug_dm_true:
|
|
if (ON_CHIP_DEBUGGER_EN = true) generate
|
|
neorv32_debug_dm_inst: neorv32_debug_dm
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock line
|
|
rstn_i => ext_rstn, -- external reset, low-active
|
|
-- debug module interface (DMI) --
|
|
dmi_rstn_i => dmi.rstn,
|
|
dmi_req_valid_i => dmi.req_valid,
|
|
dmi_req_ready_o => dmi.req_ready,
|
|
dmi_req_addr_i => dmi.req_addr,
|
|
dmi_req_op_i => dmi.req_op,
|
|
dmi_req_data_i => dmi.req_data,
|
|
dmi_resp_valid_o => dmi.resp_valid, -- response valid when set
|
|
dmi_resp_ready_i => dmi.resp_ready, -- ready to receive respond
|
|
dmi_resp_data_o => dmi.resp_data,
|
|
dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error
|
|
-- CPU bus access --
|
|
cpu_addr_i => p_bus.addr, -- address
|
|
cpu_rden_i => p_bus.re, -- read enable
|
|
cpu_wren_i => p_bus.we, -- write enable
|
|
cpu_data_i => p_bus.wdata, -- data in
|
|
cpu_data_o => dm_rdata, -- data out
|
|
cpu_ack_o => dm_ack, -- transfer acknowledge
|
|
-- CPU control --
|
|
cpu_ndmrstn_o => dci_ndmrstn, -- soc reset
|
|
cpu_halt_req_o => dci_halt_req -- request hart to halt (enter debug mode)
|
|
);
|
|
end generate;
|
|
|
|
neorv32_debug_dm_false:
|
|
if (ON_CHIP_DEBUGGER_EN = false) generate
|
|
dmi.req_ready <= '0';
|
|
dmi.resp_valid <= '0';
|
|
dmi.resp_data <= (others => '0');
|
|
dmi.resp_err <= '0';
|
|
--
|
|
dci_ndmrstn <= '0';
|
|
dci_halt_req <= '0';
|
|
dm_rdata <= (others => '0');
|
|
dm_ack <= '0';
|
|
end generate;
|
|
|
|
|
|
-- On-Chip Debugger - Debug Transport Module (DTM) ----------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_neorv32_debug_dtm_true:
|
|
if (ON_CHIP_DEBUGGER_EN = true) generate
|
|
neorv32_debug_dtm_inst: neorv32_debug_dtm
|
|
generic map (
|
|
IDCODE_VERSION => jtag_tap_idcode_version_c, -- version
|
|
IDCODE_PARTID => jtag_tap_idcode_partid_c, -- part number
|
|
IDCODE_MANID => jtag_tap_idcode_manid_c -- manufacturer id
|
|
)
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock line
|
|
rstn_i => ext_rstn, -- external reset, low-active
|
|
-- jtag connection --
|
|
jtag_trst_i => jtag_trst_i,
|
|
jtag_tck_i => jtag_tck_i,
|
|
jtag_tdi_i => jtag_tdi_i,
|
|
jtag_tdo_o => jtag_tdo_o,
|
|
jtag_tms_i => jtag_tms_i,
|
|
-- debug module interface (DMI) --
|
|
dmi_rstn_o => dmi.rstn,
|
|
dmi_req_valid_o => dmi.req_valid,
|
|
dmi_req_ready_i => dmi.req_ready, -- DMI is allowed to make new requests when set
|
|
dmi_req_addr_o => dmi.req_addr,
|
|
dmi_req_op_o => dmi.req_op, -- 0=read, 1=write
|
|
dmi_req_data_o => dmi.req_data,
|
|
dmi_resp_valid_i => dmi.resp_valid, -- response valid when set
|
|
dmi_resp_ready_o => dmi.resp_ready, -- ready to receive respond
|
|
dmi_resp_data_i => dmi.resp_data,
|
|
dmi_resp_err_i => dmi.resp_err -- 0=ok, 1=error
|
|
);
|
|
end generate;
|
|
|
|
neorv32_debug_dtm_false:
|
|
if (ON_CHIP_DEBUGGER_EN = false) generate
|
|
jtag_tdo_o <= jtag_tdi_i; -- feed-through
|
|
--
|
|
dmi.rstn <= '0';
|
|
dmi.req_valid <= '0';
|
|
dmi.req_addr <= (others => '0');
|
|
dmi.req_op <= '0';
|
|
dmi.req_data <= (others => '0');
|
|
dmi.resp_ready <= '0';
|
|
end generate;
|
|
|
|
|
end neorv32_top_rtl;
|
end neorv32_top_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
