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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_top is
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entity neorv32_top is
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- On-Chip Debugger (OCD) --
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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Line 69... |
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
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-- Internal Instruction memory (IMEM) --
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-- Internal Instruction memory (IMEM) --
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory (DMEM) --
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- Internal Cache memory (iCACHE) --
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-- Internal Cache memory (iCACHE) --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface (WISHBONE) --
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-- External memory interface (WISHBONE) --
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
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MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled)
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MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
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MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian
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MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false
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-- Stream link interface (SLINK) --
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-- Stream link interface (SLINK) --
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SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
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SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
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SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
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SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
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SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
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SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
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SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
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SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
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-- External Interrupts Controller (XIRQ) --
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-- External Interrupts Controller (XIRQ) --
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XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
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XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
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jtag_trst_i : in std_ulogic := '0'; -- low-active TAP reset (optional)
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jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
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jtag_tck_i : in std_ulogic := '0'; -- serial clock
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jtag_tck_i : in std_ulogic := 'U'; -- serial clock
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jtag_tdi_i : in std_ulogic := '0'; -- serial data input
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jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
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jtag_tdo_o : out std_ulogic; -- serial data output
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jtag_tdo_o : out std_ulogic; -- serial data output
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jtag_tms_i : in std_ulogic := '0'; -- mode select
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jtag_tms_i : in std_ulogic := 'U'; -- mode select
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-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
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wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_stb_o : out std_ulogic; -- strobe
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wb_stb_o : out std_ulogic; -- strobe
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_lock_o : out std_ulogic; -- exclusive access request
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wb_lock_o : out std_ulogic; -- exclusive access request
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wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
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wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge
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wb_err_i : in std_ulogic := '0'; -- transfer error
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wb_err_i : in std_ulogic := 'L'; -- transfer error
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fence_o : out std_ulogic; -- indicates an executed FENCE operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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slink_tx_dat_o : out sdata_8x32_t; -- output data
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
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slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- ready to send
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slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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slink_rx_dat_i : in sdata_8x32_t := (others => (others => '0')); -- input data
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slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data
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slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- valid input
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slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
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slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
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slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
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-- GPIO (available if IO_GPIO_EN = true) --
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
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gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
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gpio_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- parallel input
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gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
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uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
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uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
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uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
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-- secondary UART1 (available if IO_UART1_EN = true) --
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-- secondary UART1 (available if IO_UART1_EN = true) --
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uart1_txd_o : out std_ulogic; -- UART1 send data
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uart1_txd_o : out std_ulogic; -- UART1 send data
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uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
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uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
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uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
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uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
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uart1_cts_i : in std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
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uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
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-- SPI (available if IO_SPI_EN = true) --
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-- SPI (available if IO_SPI_EN = true) --
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
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spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
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-- TWI (available if IO_TWI_EN = true) --
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_io : inout std_logic; -- twi serial data line
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twi_sda_io : inout std_logic := 'U'; -- twi serial data line
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twi_scl_io : inout std_logic; -- twi serial clock line
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twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
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pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
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cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_ulogic; -- async serial data line
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neoled_o : out std_ulogic; -- async serial data line
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-- System time --
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-- System time --
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels
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xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
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-- CPU interrupts --
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-- CPU interrupts --
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nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
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nm_irq_i : in std_ulogic := 'L'; -- non-maskable interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
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);
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);
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end neorv32_top;
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end neorv32_top;
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architecture neorv32_top_rtl of neorv32_top is
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architecture neorv32_top_rtl of neorv32_top is
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| Line 319... |
Line 324... |
signal neoled_irq : std_ulogic;
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signal neoled_irq : std_ulogic;
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signal slink_tx_irq : std_ulogic;
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signal slink_tx_irq : std_ulogic;
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signal slink_rx_irq : std_ulogic;
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signal slink_rx_irq : std_ulogic;
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signal xirq_irq : std_ulogic;
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signal xirq_irq : std_ulogic;
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-- machine (CPU) interrupts --
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signal x_nm_irq, nm_irq_ff : std_ulogic;
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signal x_mtime_irq, mtime_irq_ff : std_ulogic;
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signal x_msw_irq, msw_irq_ff : std_ulogic;
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signal x_mext_irq, mext_irq_ff : std_ulogic;
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-- misc --
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-- misc --
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
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signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
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signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
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signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
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| Line 349... |
Line 360... |
severity note;
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severity note;
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- clock --
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assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
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-- boot configuration --
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-- boot configuration --
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assert not (INT_BOOTLOADER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note;
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assert not (INT_BOOTLOADER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note;
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM)." severity note;
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM)." severity note;
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-external (I)MEM)." severity note;
|
assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-external (I)MEM)." severity note;
|
--
|
--
|
| Line 460... |
Line 468... |
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
|
CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
|
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
|
| Line 499... |
Line 508... |
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => mtime_time, -- current system time
|
time_i => mtime_time, -- current system time
|
-- non-maskable interrupt --
|
-- non-maskable interrupt --
|
nm_irq_i => nm_irq_i, -- NMI
|
nm_irq_i => x_nm_irq, -- NMI
|
-- interrupts (risc-v compliant) --
|
msw_irq_i => x_msw_irq, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
mext_irq_i => x_mext_irq, -- machine external interrupt request
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_i => fast_irq, -- fast interrupt trigger
|
-- debug mode (halt) request --
|
-- debug mode (halt) request --
|
db_halt_req_i => dci_halt_req
|
db_halt_req_i => dci_halt_req
|
| Line 518... |
Line 526... |
|
|
-- advanced memory control --
|
-- advanced memory control --
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
|
-- external machine-level (CPU) interrupts --
|
|
nm_irq_ff <= nm_irq_i when rising_edge(clk_i);
|
|
mtime_irq_ff <= mtime_irq_i when rising_edge(clk_i);
|
|
msw_irq_ff <= msw_irq_i when rising_edge(clk_i);
|
|
mext_irq_ff <= mext_irq_i when rising_edge(clk_i);
|
|
-- rising-edge detector --
|
|
x_nm_irq <= nm_irq_i and (not nm_irq_ff);
|
|
x_mtime_irq <= mtime_irq_i and (not mtime_irq_ff);
|
|
x_msw_irq <= msw_irq_i and (not msw_irq_ff);
|
|
x_mext_irq <= mext_irq_i and (not mext_irq_ff);
|
|
|
-- fast interrupts --
|
-- fast interrupts --
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog timeout
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(01) <= cfs_irq; -- custom functions subsystem
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
|
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) data received
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
|
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) sending done
|
| Line 532... |
Line 551... |
fast_irq(08) <= xirq_irq; -- external interrupt controller
|
fast_irq(08) <= xirq_irq; -- external interrupt controller
|
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
|
fast_irq(09) <= neoled_irq; -- NEOLED buffer free
|
fast_irq(10) <= slink_rx_irq; -- SLINK data received
|
fast_irq(10) <= slink_rx_irq; -- SLINK data received
|
fast_irq(11) <= slink_tx_irq; -- SLINK data send
|
fast_irq(11) <= slink_tx_irq; -- SLINK data send
|
--
|
--
|
fast_irq(15 downto 12) <= (others => '0'); -- reserved
|
fast_irq(12) <= '0'; -- reserved
|
|
fast_irq(13) <= '0'; -- reserved
|
|
fast_irq(14) <= '0'; -- reserved
|
|
fast_irq(15) <= '0'; -- reserved
|
|
|
|
|
-- CPU Instruction Cache ------------------------------------------------------------------
|
-- CPU Instruction Cache ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_icache_inst_true:
|
neorv32_icache_inst_true:
|
| Line 776... |
Line 798... |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
-- Bus Timeout --
|
-- Interface Configuration --
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
PIPE_MODE => MEM_EXT_PIPE_MODE, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
|
|
BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
|
|
ASYNC_RX => MEM_EXT_ASYNC_RX -- use register buffer for RX data when false
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset line, low-active
|
rstn_i => sys_rstn, -- global reset line, low-active
|
| Line 964... |
Line 989... |
|
|
neorv32_mtime_inst_false:
|
neorv32_mtime_inst_false:
|
if (IO_MTIME_EN = false) generate
|
if (IO_MTIME_EN = false) generate
|
resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c;
|
mtime_time <= mtime_i; -- use external machine timer time signal
|
mtime_time <= mtime_i; -- use external machine timer time signal
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
mtime_irq <= x_mtime_irq; -- use external machine timer interrupt
|
end generate;
|
end generate;
|
|
|
|
|
-- system time output LO --
|
-- system time output LO --
|
mtime_sync: process(clk_i)
|
mtime_sync: process(clk_i)
|
| Line 1214... |
Line 1239... |
-- Smart LED (WS2811/WS2812) Interface (NEOLED) -------------------------------------------
|
-- Smart LED (WS2811/WS2812) Interface (NEOLED) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_neoled_inst_true:
|
neorv32_neoled_inst_true:
|
if (IO_NEOLED_EN = true) generate
|
if (IO_NEOLED_EN = true) generate
|
neorv32_neoled_inst: neorv32_neoled
|
neorv32_neoled_inst: neorv32_neoled
|
|
generic map (
|
|
FIFO_DEPTH => IO_NEOLED_TX_FIFO -- TX FIFO depth (1..32k, power of two)
|
|
)
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
| Line 1344... |
Line 1372... |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
|
ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface?
|
|
MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian
|
-- On-Chip Debugger --
|
-- On-Chip Debugger --
|
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD?
|
ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
