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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - External Interrupt Controller (XIRQ) >> #
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-- # << NEORV32 - External Interrupt Controller (XIRQ) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels #
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-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels #
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-- # are supported that get prioritized into a single CPU interrupt. #
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-- # are supported that get (optionally) prioritized into a single CPU interrupt. #
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-- # #
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-- # #
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-- # The actual trigger configuration has to be done before synthesis using the XIRQ_TRIGGER_TYPE #
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-- # The actual trigger configuration has to be done before synthesis using the XIRQ_TRIGGER_TYPE #
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-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level, #
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-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level, #
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-- # high-level, falling-edge and rising-edge triggers. #
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-- # high-level, falling-edge and rising-edge triggers. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_xirq is
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entity neorv32_xirq is
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generic (
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generic (
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XIRQ_NUM_CH : natural := 32; -- number of external IRQ channels (0..32)
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XIRQ_NUM_CH : natural; -- number of external IRQ channels (0..32)
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0); -- trigger type: 0=level, 1=edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := (others => '1') -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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);
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);
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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