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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [sim/] [simple/] [neorv32_tb.simple.vhd] - Diff between revs 70 and 72
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| Rev 70 |
Rev 72 |
| Line 185... |
Line 185... |
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
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CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zxcfu => true, -- implement custom (instr.) functions unit?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
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FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
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CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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