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// #################################################################################################
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// #################################################################################################
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// # << NEORV32 - Bootloader >> #
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// # << NEORV32 - Bootloader >> #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # BSD 3-Clause License #
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// # #
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// # #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # permitted provided that the following conditions are met: #
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// # #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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ERROR_SIZE = 1, /**< 1: Insufficient instruction memory capacity */
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ERROR_SIZE = 1, /**< 1: Insufficient instruction memory capacity */
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ERROR_CHECKSUM = 2, /**< 2: Checksum error in executable */
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ERROR_CHECKSUM = 2, /**< 2: Checksum error in executable */
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ERROR_FLASH = 3 /**< 3: SPI flash access error */
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ERROR_FLASH = 3 /**< 3: SPI flash access error */
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};
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};
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/**********************************************************************//**
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* Error messages
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**************************************************************************/
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const char error_message[4][24] = {
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"exe signature fail",
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"exceeding IMEM capacity",
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"checksum fail",
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"SPI flash access failed"
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* SPI flash commands
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* SPI flash commands
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**************************************************************************/
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**************************************************************************/
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enum SPI_FLASH_CMD {
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enum SPI_FLASH_CMD {
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EXE_OFFSET_DATA = 12, /**< Offset in bytes from start to data (32-bit) */
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EXE_OFFSET_DATA = 12, /**< Offset in bytes from start to data (32-bit) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* Valid executable identification signature.
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* Valid executable identification signature
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**************************************************************************/
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**************************************************************************/
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#define EXE_SIGNATURE 0x4788CAFE
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#define EXE_SIGNATURE 0x4788CAFE
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/**********************************************************************//**
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/**********************************************************************//**
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#if (UART_EN != 0)
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#if (UART_EN != 0)
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// setup UART0 (primary UART, no parity bit, no hardware flow control)
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// setup UART0 (primary UART, no parity bit, no hardware flow control)
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neorv32_uart0_setup(UART_BAUD, PARITY_NONE, FLOW_CONTROL_NONE);
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neorv32_uart0_setup(UART_BAUD, PARITY_NONE, FLOW_CONTROL_NONE);
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#endif
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#endif
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// Configure machine system timer interrupt for ~2Hz
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// Configure machine system timer interrupt
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if (neorv32_mtime_available()) {
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if (neorv32_mtime_available()) {
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neorv32_mtime_set_timecmp(neorv32_cpu_get_systime() + (NEORV32_SYSINFO.CLK/4));
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neorv32_mtime_set_timecmp(0 + (NEORV32_SYSINFO.CLK/4));
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// active timer IRQ
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// active timer IRQ
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source only!
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source only!
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neorv32_cpu_eint(); // enable global interrupts
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neorv32_cpu_eint(); // enable global interrupts
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}
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}
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PRINT_TEXT("\n\n\n<< NEORV32 Bootloader >>\n\n"
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PRINT_TEXT("\n\n\n<< NEORV32 Bootloader >>\n\n"
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"BLDV: "__DATE__"\nHWV: ");
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"BLDV: "__DATE__"\nHWV: ");
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MIMPID));
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MIMPID));
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PRINT_TEXT("\nCLK: ");
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PRINT_TEXT("\nCLK: ");
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PRINT_XNUM(NEORV32_SYSINFO.CLK);
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PRINT_XNUM(NEORV32_SYSINFO.CLK);
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PRINT_TEXT("\nMISA: ");
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PRINT_TEXT("\nISA: ");
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MISA));
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MISA));
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PRINT_TEXT("\nCPU: ");
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PRINT_TEXT(" + ");
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PRINT_XNUM(NEORV32_SYSINFO.CPU);
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MXISA));
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PRINT_TEXT("\nSOC: ");
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PRINT_TEXT("\nSOC: ");
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PRINT_XNUM(NEORV32_SYSINFO.SOC);
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PRINT_XNUM(NEORV32_SYSINFO.SOC);
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PRINT_TEXT("\nIMEM: ");
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PRINT_TEXT("\nIMEM: ");
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PRINT_XNUM(NEORV32_SYSINFO.IMEM_SIZE);
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PRINT_XNUM(NEORV32_SYSINFO.IMEM_SIZE); PRINT_TEXT(" bytes @");
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PRINT_TEXT(" bytes @");
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PRINT_XNUM(NEORV32_SYSINFO.ISPACE_BASE);
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PRINT_XNUM(NEORV32_SYSINFO.ISPACE_BASE);
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PRINT_TEXT("\nDMEM: ");
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PRINT_TEXT("\nDMEM: ");
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PRINT_XNUM(NEORV32_SYSINFO.DMEM_SIZE);
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PRINT_XNUM(NEORV32_SYSINFO.DMEM_SIZE);
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PRINT_TEXT(" bytes @");
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PRINT_TEXT(" bytes @");
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PRINT_XNUM(NEORV32_SYSINFO.DSPACE_BASE);
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PRINT_XNUM(NEORV32_SYSINFO.DSPACE_BASE);
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// ------------------------------------------------
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// ------------------------------------------------
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#if (SPI_EN != 0)
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#if (SPI_EN != 0)
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#if (AUTO_BOOT_TIMEOUT != 0)
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#if (AUTO_BOOT_TIMEOUT != 0)
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if (neorv32_mtime_available()) {
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if (neorv32_mtime_available()) {
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PRINT_TEXT("\n\nAutoboot in "xstr(AUTO_BOOT_TIMEOUT)"s. Press key to abort.\n");
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PRINT_TEXT("\n\nAutoboot in "xstr(AUTO_BOOT_TIMEOUT)"s. Press any key to abort.\n");
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uint64_t timeout_time = neorv32_cpu_get_systime() + (uint64_t)(AUTO_BOOT_TIMEOUT * NEORV32_SYSINFO.CLK);
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uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTO_BOOT_TIMEOUT * NEORV32_SYSINFO.CLK);
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while(1){
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while(1){
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if (neorv32_uart0_available()) { // wait for any key to be pressed
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if (neorv32_uart0_available()) { // wait for any key to be pressed
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if (neorv32_uart0_char_received()) {
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if (neorv32_uart0_char_received()) {
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break;
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break;
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}
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}
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}
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}
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if (neorv32_cpu_get_systime() >= timeout_time) { // timeout? start auto boot sequence
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if (neorv32_mtime_get_time() >= timeout_time) { // timeout? start auto boot sequence
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get_exe(EXE_STREAM_FLASH); // try booting from flash
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get_exe(EXE_STREAM_FLASH); // try booting from flash
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PRINT_TEXT("\n");
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PRINT_TEXT("\n");
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start_app();
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start_app();
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while(1);
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while(1);
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}
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}
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}
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}
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else {
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else {
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start_app();
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start_app();
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}
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}
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}
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}
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else if (c == '?') {
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PRINT_TEXT("(c) by Stephan Nolting\nhttps://github.com/stnolting/neorv32");
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}
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else { // unknown command
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else { // unknown command
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PRINT_TEXT("Invalid CMD");
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PRINT_TEXT("Invalid CMD");
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}
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}
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}
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}
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neorv32_gpio_pin_toggle(STATUS_LED_PIN); // toggle status LED
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neorv32_gpio_pin_toggle(STATUS_LED_PIN); // toggle status LED
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}
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}
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#endif
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#endif
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// set time for next IRQ
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// set time for next IRQ
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if (neorv32_mtime_available()) {
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if (neorv32_mtime_available()) {
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neorv32_mtime_set_timecmp(neorv32_cpu_get_systime() + (NEORV32_SYSINFO.CLK/4));
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neorv32_mtime_set_timecmp(neorv32_mtime_get_timecmp() + (NEORV32_SYSINFO.CLK/4));
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}
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}
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}
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}
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// Bus store access error during get_exe
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// Bus store access error during get_exe
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else if ((cause == TRAP_CODE_S_ACCESS) && (getting_exe)) {
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else if ((cause == TRAP_CODE_S_ACCESS) && (getting_exe)) {
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// Anything else (that was not expected); output exception notifier and try to resume
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// Anything else (that was not expected); output exception notifier and try to resume
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else {
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else {
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register uint32_t epc = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t epc = neorv32_cpu_csr_read(CSR_MEPC);
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#if (UART_EN != 0)
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#if (UART_EN != 0)
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if (neorv32_uart0_available()) {
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if (neorv32_uart0_available()) {
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PRINT_TEXT("\n[ERR ");
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PRINT_TEXT("\n[ERROR - Unexpected exception! mcause=");
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PRINT_XNUM(cause); // MCAUSE
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PRINT_XNUM(cause); // MCAUSE
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PRINT_PUTC(' ');
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PRINT_TEXT(" mepc=");
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PRINT_XNUM(epc); // MEPC
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PRINT_XNUM(epc); // MEPC
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PRINT_PUTC(' ');
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PRINT_TEXT(" mtval=");
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MTVAL)); // MTVAL
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PRINT_XNUM(neorv32_cpu_csr_read(CSR_MTVAL)); // MTVAL
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PRINT_TEXT("]\n");
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PRINT_TEXT("] trying to resume...\n");
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}
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}
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#endif
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#endif
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neorv32_cpu_csr_write(CSR_MEPC, epc + 4); // advance to next instruction
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neorv32_cpu_csr_write(CSR_MEPC, epc + 4); // advance to next instruction
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}
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Output system error ID and stall.
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* Output system error ID and stall.
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*
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*
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* @param[in] err_code Error code. See #ERROR_CODES.
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* @param[in] err_code Error code. See #ERROR_CODES and #error_message.
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**************************************************************************/
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**************************************************************************/
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void system_error(uint8_t err_code) {
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void system_error(uint8_t err_code) {
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PRINT_TEXT("\a\nERROR_"); // output error code with annoying bell sound
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PRINT_TEXT("\a\nERROR_"); // output error code with annoying bell sound
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PRINT_PUTC('0' + ((char)err_code));
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PRINT_PUTC('0' + ((char)err_code));
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PRINT_PUTC(':');
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PRINT_PUTC(' ');
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PRINT_TEXT(error_message[err_code]);
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neorv32_cpu_dint(); // deactivate IRQs
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neorv32_cpu_dint(); // deactivate IRQs
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#if (STATUS_LED_EN != 0)
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#if (STATUS_LED_EN != 0)
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if (neorv32_gpio_available()) {
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if (neorv32_gpio_available()) {
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neorv32_gpio_port_set(1 << STATUS_LED_PIN); // permanently light up status LED
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neorv32_gpio_port_set(1 << STATUS_LED_PIN); // permanently light up status LED
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