| Line 481... |
Line 481... |
else {
|
else {
|
test_fail();
|
test_fail();
|
}
|
}
|
|
|
|
|
// ----------------------------------------------------------
|
//// ----------------------------------------------------------
|
// No "real" CSR write access (because rs1 = r0)
|
//// No "real" CSR write access (because rs1 = r0)
|
// ----------------------------------------------------------
|
//// ----------------------------------------------------------
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
//neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test);
|
//PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test);
|
|
//
|
cnt_test++;
|
//cnt_test++;
|
|
//
|
// time CSR is read-only, but no actual write is performed because rs1=r0
|
//// time CSR is read-only, but no actual write is performed because rs1=r0
|
// -> should cause no exception
|
//// -> should cause no exception
|
asm volatile("csrrs zero, time, zero");
|
//asm volatile("csrrs zero, time, zero");
|
|
//
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
//if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
test_ok();
|
// test_ok();
|
}
|
//}
|
else {
|
//else {
|
test_fail();
|
// test_fail();
|
}
|
//}
|
|
|
|
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
// Unaligned instruction address
|
// Unaligned instruction address
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
| Line 1122... |
Line 1122... |
cnt_test++;
|
cnt_test++;
|
|
|
// configure SPI
|
// configure SPI
|
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 0);
|
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 0);
|
|
|
// trigger SPI IRQ
|
|
neorv32_spi_trans(0);
|
|
// enable fast interrupt
|
// enable fast interrupt
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
|
|
|
|
// trigger SPI IRQ
|
|
neorv32_spi_trans(0);
|
while(neorv32_spi_busy()); // wait for current transfer to finish
|
while(neorv32_spi_busy()); // wait for current transfer to finish
|
|
|
// wait some time for the IRQ to arrive the CPU
|
// wait some time for the IRQ to arrive the CPU
|
asm volatile("nop");
|
asm volatile("nop");
|
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
|
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
|
| Line 1153... |
Line 1154... |
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
PRINT_STANDARD("[%i] FIRQ7 (TWI): ", cnt_test);
|
PRINT_STANDARD("[%i] FIRQ7 (TWI): ", cnt_test);
|
|
|
cnt_test++;
|
cnt_test++;
|
|
|
// configure TWI, fastest clock, no peripheral clock stretching
|
// configure TWI, fastest clock
|
neorv32_twi_setup(CLK_PRSC_2, 0);
|
neorv32_twi_setup(CLK_PRSC_2);
|
|
|
|
// enable TWI FIRQ
|
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
|
|
|
// trigger TWI IRQ
|
// trigger TWI IRQ
|
neorv32_twi_generate_start();
|
neorv32_twi_generate_start();
|
neorv32_twi_trans(0);
|
|
neorv32_twi_generate_stop();
|
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
|
|
|
|
// wait some time for the IRQ to arrive the CPU
|
// wait some time for the IRQ to arrive the CPU
|
asm volatile("nop");
|
asm volatile("nop");
|
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
|
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
|
|
|
| Line 1222... |
Line 1223... |
|
|
|
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
// Fast interrupt channel 9 (NEOLED)
|
// Fast interrupt channel 9 (NEOLED)
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
PRINT_STANDARD("[%i] FIRQ9 (NEOLED): skipped\n", cnt_test);
|
if (neorv32_neoled_available()) {
|
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
|
PRINT_STANDARD("[%i] FIRQ9 (NEOLED): ", cnt_test);
|
|
|
|
cnt_test++;
|
|
|
|
// enable fast interrupt
|
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ9E);
|
|
|
|
// configure NEOLED
|
|
neorv32_neoled_setup(CLK_PRSC_2, 0, 0, 0);
|
|
|
|
// send dummy data
|
|
neorv32_neoled_write_nonblocking(0);
|
|
|
|
// wait some time for the IRQ to arrive the CPU
|
|
asm volatile("nop");
|
|
neorv32_cpu_irq_disable(CSR_MIE_FIRQ9E);
|
|
|
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_9) {
|
|
test_ok();
|
|
}
|
|
else {
|
|
test_fail();
|
|
}
|
|
|
|
// no more NEOLED interrupts
|
|
neorv32_neoled_disable();
|
|
}
|
|
|
|
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
// Fast interrupt channel 10 & 11 (SLINK)
|
// Fast interrupt channel 10 & 11 (SLINK)
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
| Line 1234... |
Line 1263... |
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
PRINT_STANDARD("[%i] FIRQ10 & 11 (SLINK): ", cnt_test);
|
PRINT_STANDARD("[%i] FIRQ10 & 11 (SLINK): ", cnt_test);
|
|
|
cnt_test++;
|
cnt_test++;
|
|
|
// enable SLINK
|
|
neorv32_slink_enable();
|
|
|
|
// configure SLINK IRQs
|
// configure SLINK IRQs
|
neorv32_slink_tx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_TX_NOT_FULL);
|
neorv32_slink_tx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_TX_NOT_FULL);
|
neorv32_slink_rx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_RX_NOT_EMPTY);
|
neorv32_slink_rx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_RX_NOT_EMPTY);
|
|
|
|
// enable SLINK
|
|
neorv32_slink_enable();
|
|
|
// enable SLINK FIRQs
|
// enable SLINK FIRQs
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ10E);
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ10E);
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ11E);
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ11E);
|
|
|
tmp_a = 0; // error counter
|
tmp_a = 0; // error counter
|
| Line 1304... |
Line 1333... |
cnt_test++;
|
cnt_test++;
|
|
|
// enable GPTMR FIRQ
|
// enable GPTMR FIRQ
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ12E);
|
neorv32_cpu_irq_enable(CSR_MIE_FIRQ12E);
|
|
|
// configure timer IRQ for one-shot mode after 2*4 clock cycles
|
// configure timer IRQ for one-shot mode after 2*3 clock cycles
|
neorv32_gptmr_setup(CLK_PRSC_2, 0, 4);
|
neorv32_gptmr_setup(CLK_PRSC_2, 0, 3);
|
|
|
// wait some time for the IRQ to arrive the CPU
|
// wait some time for the IRQ to arrive the CPU
|
asm volatile("nop");
|
asm volatile("nop");
|
asm volatile("nop");
|
asm volatile("nop");
|
|
|
