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// Standard libraries
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// Standard libraries
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#include <stdint.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <limits.h>
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#include <unistd.h>
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#include <stdlib.h>
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/**********************************************************************//**
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/**********************************************************************//**
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* Available CPU Control and Status Registers (CSRs)
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* Available CPU Control and Status Registers (CSRs)
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**************************************************************************/
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**************************************************************************/
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CSR_PMPADDR60 = 0x3ec, /**< 0x3ec - pmpaddr60 (r/w): Physical memory protection address register 60 */
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CSR_PMPADDR60 = 0x3ec, /**< 0x3ec - pmpaddr60 (r/w): Physical memory protection address register 60 */
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CSR_PMPADDR61 = 0x3ed, /**< 0x3ed - pmpaddr61 (r/w): Physical memory protection address register 61 */
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CSR_PMPADDR61 = 0x3ed, /**< 0x3ed - pmpaddr61 (r/w): Physical memory protection address register 61 */
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CSR_PMPADDR62 = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */
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CSR_PMPADDR62 = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */
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CSR_PMPADDR63 = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */
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CSR_PMPADDR63 = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */
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CSR_TSELECT = 0x7a0, /**< 0x7a0 - tselect (r/(w)): Trigger select */
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CSR_TDATA1 = 0x7a1, /**< 0x7a1 - tdata1 (r/(w)): Trigger data register 0 */
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CSR_TDATA2 = 0x7a2, /**< 0x7a2 - tdata2 (r/(w)): Trigger data register 1 */
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CSR_TDATA3 = 0x7a3, /**< 0x7a3 - tdata3 (r/(w)): Trigger data register 2 */
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CSR_TINFO = 0x7a4, /**< 0x7a4 - tinfo (r/(w)): Trigger info */
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CSR_TCONTROL = 0x7a5, /**< 0x7a5 - tcontrol (r/(w)): Trigger control */
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CSR_MCONTEXT = 0x7a8, /**< 0x7a8 - mcontext (r/(w)): Machine context register */
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CSR_SCONTEXT = 0x7aa, /**< 0x7aa - scontext (r/(w)): Supervisor context register */
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//CSR_DCSR = 0x7b0, /**< 0x7b0 - dcsr (-/-): Debug status and control register */
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//CSR_DPC = 0x7b1, /**< 0x7b1 - dpc (-/-): Debug program counter */
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//CSR_DSCRATCHC = 0x7b2, /**< 0x7b2 - dscratch (-/-): Debug scratch register */
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
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CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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CSR_MHPMCOUNTER3 = 0xb03, /**< 0xb03 - mhpmcounter3 (r/w): Machine hardware performance monitor 3 counter low word */
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CSR_MHPMCOUNTER3 = 0xb03, /**< 0xb03 - mhpmcounter3 (r/w): Machine hardware performance monitor 3 counter low word */
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CSR_MHPMCOUNTER4 = 0xb04, /**< 0xb04 - mhpmcounter4 (r/w): Machine hardware performance monitor 4 counter low word */
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CSR_MHPMCOUNTER4 = 0xb04, /**< 0xb04 - mhpmcounter4 (r/w): Machine hardware performance monitor 4 counter low word */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MCONFIGPTR = 0xf15 /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
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CSR_MCONFIGPTR = 0xf15, /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
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CSR_MXISA = 0xfc0 /**< 0xfc0 - xisa (r/-): NEORV32-specific machine "extended CPU ISA and extensions" */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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CSR_MISA_MXL_HI = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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CSR_MISA_MXL_HI = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mxisa</b> CSR (r/-): Machine _extended_ instruction set extensions (NEORV32-spec.)
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**************************************************************************/
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enum NEORV32_CSR_XISA_enum {
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// ISA (sub-)extensions
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CSR_MXISA_ZICSR = 0, /**< CPU mxisa CSR (0): privileged architecture (r/-)*/
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CSR_MXISA_ZIFENCEI = 1, /**< CPU mxisa CSR (1): instruction stream sync (r/-)*/
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CSR_MXISA_ZMMUL = 2, /**< CPU mxisa CSR (2): hardware mul/div (r/-)*/
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CSR_MXISA_ZXCFU = 3, /**< CPU mxisa CSR (3): custom RISC-V instructions (r/-)*/
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CSR_MXISA_ZFINX = 5, /**< CPU mxisa CSR (5): FPU using x registers, "F-alternative" (r/-)*/
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CSR_MXISA_ZXSCNT = 6, /**< CPU mxisa CSR (6): reduced-size CPU counters (from Zicntr) (r/-)*/
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CSR_MXISA_ZICNTR = 7, /**< CPU mxisa CSR (7): base instructions, cycle and time CSRs (r/-)*/
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CSR_MXISA_PMP = 8, /**< CPU mxisa CSR (8): physical memory protection (also "Smpmp") (r/-)*/
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CSR_MXISA_ZIHPM = 9, /**< CPU mxisa CSR (9): hardware performance monitors (r/-)*/
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CSR_MXISA_DEBUGMODE = 10, /**< CPU mxisa CSR (10): RISC-V debug mode (r/-)*/
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// Tuning options
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CSR_MXISA_FASTMUL = 30, /**< CPU mxisa CSR (30): DSP-based multiplication (M extensions only) (r/-)*/
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CSR_MXISA_FASTSHIFT = 31 /**< CPU mxisa CSR (31): parallel logic for shifts (barrel shifters) (r/-)*/
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};
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/**********************************************************************//**
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* CPU <b>mhpmevent</b> hardware performance monitor events
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* CPU <b>mhpmevent</b> hardware performance monitor events
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_HPMCNT_EVENT_enum {
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enum NEORV32_HPMCNT_EVENT_enum {
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HPMCNT_EVENT_CY = 0, /**< CPU mhpmevent CSR (0): Active cycle */
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HPMCNT_EVENT_CY = 0, /**< CPU mhpmevent CSR (0): Active cycle */
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HPMCNT_EVENT_IR = 2, /**< CPU mhpmevent CSR (2): Retired instruction */
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HPMCNT_EVENT_IR = 2, /**< CPU mhpmevent CSR (2): Retired instruction */
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** SYSINFO module prototype - whole module is read-only */
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/** SYSINFO module prototype - whole module is read-only */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef struct __attribute__((packed,aligned(4))) {
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const uint32_t CLK; /**< offset 0: clock speed in Hz */
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const uint32_t CLK; /**< offset 0: clock speed in Hz */
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const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */
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const uint32_t reserved; /**< offset 4: reserved */
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const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
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const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
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const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
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const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
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const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */
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const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */
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const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
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const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
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const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */
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const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */
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} neorv32_sysinfo_t;
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} neorv32_sysinfo_t;
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/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
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/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
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#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL)))
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#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL)))
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/** NEORV32_SYSINFO.CPU (r/-): Implemented CPU sub-extensions/features */
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enum NEORV32_SYSINFO_CPU_enum {
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SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
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SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
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SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basic CPU counters available when set (r/-) */
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SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
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SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
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SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
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SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
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SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */
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};
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/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */
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/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */
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enum NEORV32_SYSINFO_SOC_enum {
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enum NEORV32_SYSINFO_SOC_enum {
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SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
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SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
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SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
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SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
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SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
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SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
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};
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};
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/**@}*/
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/**@}*/
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Include all IO driver headers
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// Include all system header files
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// cpu core
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#include "neorv32_cpu.h"
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// intrinsics
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// intrinsics
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#include "neorv32_intrinsics.h"
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#include "neorv32_intrinsics.h"
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// cpu core
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#include "neorv32_cpu.h"
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#include "neorv32_cpu_cfu.h"
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// neorv32 runtime environment
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// neorv32 runtime environment
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#include "neorv32_rte.h"
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#include "neorv32_rte.h"
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// io/peripheral devices
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// io/peripheral devices
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#include "neorv32_cfs.h"
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#include "neorv32_cfs.h"
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