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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] [neorv32_cpu.h] - Diff between revs 65 and 68
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| Rev 65 |
Rev 68 |
| Line 271... |
Line 271... |
* Enable global CPU interrupts (via MIE flag in mstatus CSR).
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* Enable global CPU interrupts (via MIE flag in mstatus CSR).
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**************************************************************************/
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
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inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
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asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
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asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
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asm volatile ("nop");
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asm volatile ("nop");
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable global CPU interrupts (via MIE flag in mstatus CSR).
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* Disable global CPU interrupts (via MIE flag in mstatus CSR).
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**************************************************************************/
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
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inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
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asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
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asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
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asm volatile ("nop");
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asm volatile ("nop");
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Trigger breakpoint exception (via EBREAK instruction).
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* Trigger breakpoint exception (via EBREAK instruction).
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