| Line 280... |
Line 280... |
// CPU configuration
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// CPU configuration
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neorv32_uart_printf("\n=== << CPU >> ===\n");
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neorv32_uart_printf("\n=== << CPU >> ===\n");
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// ID
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// ID
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neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
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neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
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neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
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neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
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tmp = neorv32_cpu_csr_read(CSR_MARCHID);
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tmp = neorv32_cpu_csr_read(CSR_MARCHID);
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neorv32_uart_printf("Architecture ID: 0x%x", tmp);
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neorv32_uart_printf("Architecture ID: 0x%x", tmp);
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if (tmp == NEORV32_ARCHID) {
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if (tmp == NEORV32_ARCHID) {
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| Line 351... |
Line 350... |
neorv32_uart_printf("Zba ");
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neorv32_uart_printf("Zba ");
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}
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}
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if (tmp & (1<<CSR_MZEXT_ZFINX)) {
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if (tmp & (1<<CSR_MZEXT_ZFINX)) {
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neorv32_uart_printf("Zfinx ");
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neorv32_uart_printf("Zfinx ");
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}
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}
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if (tmp & (1<<CSR_MZEXT_ZXNOCNT)) {
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neorv32_uart_printf("Zxnocnt(!) ");
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}
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if (tmp & (1<<CSR_MZEXT_ZXSCNT)) {
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neorv32_uart_printf("Zxscnt(!) ");
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}
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// check physical memory protection
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// check physical memory protection
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neorv32_uart_printf("\nPMP: ");
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neorv32_uart_printf("\nPMP: ");
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uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
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uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
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if (pmp_num_regions != 0) {
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if (pmp_num_regions != 0) {
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| Line 363... |
Line 368... |
else {
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else {
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neorv32_uart_printf("not implemented\n");
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neorv32_uart_printf("not implemented\n");
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}
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}
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// check hardware performance monitors
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// check hardware performance monitors
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neorv32_uart_printf("HPM Counters: %u\n", neorv32_cpu_hpm_get_counters());
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neorv32_uart_printf("HPM Counters: %ux, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
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// Memory configuration
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// Memory configuration
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neorv32_uart_printf("\n=== << Memory Configuration >> ===\n");
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neorv32_uart_printf("\n=== << Memory Configuration >> ===\n");
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neorv32_uart_printf("Instr. base address: 0x%x\n", SYSINFO_ISPACE_BASE);
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neorv32_uart_printf("Instr. base address: 0x%x\n", SYSINFO_ISPACE_BASE);
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// IMEM
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neorv32_uart_printf("Internal IMEM: ");
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neorv32_uart_printf("Internal IMEM: ");
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM)) {
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neorv32_uart_printf("IMEM size: %u bytes\n", SYSINFO_IMEM_SIZE);
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neorv32_uart_printf("yes, %u bytes", SYSINFO_IMEM_SIZE);
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neorv32_uart_printf("Internal IMEM as ROM: ");
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM)) {
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
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neorv32_uart_printf(", read-only (ROM)");
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}
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}
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else {
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neorv32_uart_printf("no");
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}
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neorv32_uart_printf("\n");
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// DMEM
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neorv32_uart_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE);
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neorv32_uart_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE);
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neorv32_uart_printf("Internal DMEM: ");
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neorv32_uart_printf("Internal DMEM: ");
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM)) { neorv32_uart_printf("yes, %u bytes\n", SYSINFO_DMEM_SIZE); }
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neorv32_uart_printf("DMEM size: %u bytes\n", SYSINFO_DMEM_SIZE);
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else { neorv32_uart_printf("no\n"); }
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// i-cache
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neorv32_uart_printf("Internal i-cache: ");
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neorv32_uart_printf("Internal i-cache: ");
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE));
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) {
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) {
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neorv32_uart_printf("- ");
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neorv32_uart_printf("- ");
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