| Line 69... |
Line 69... |
// PASS RB 11_111 // ALUOP <- RB, FLAGS <- RA
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// PASS RB 11_111 // ALUOP <- RB, FLAGS <- RA
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//
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//
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//
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//
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// FLAGS: X X X X OF DF IF TF | SF ZF X AF X PF X CF
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// FLAGS: X X X X OF DF IF TF | SF ZF X AF X PF X CF
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//
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//
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// 09Feb2013 - fixed DAA,DAS bug
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_ALU(
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module Next186_ALU(
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input [15:0] RA,
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input [15:0] RA,
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| Line 108... |
Line 109... |
wire parity = ~^ALUOUT[7:0];
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wire parity = ~^ALUOUT[7:0];
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wire zero8 = ~|ALUOUT[7:0];
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wire zero8 = ~|ALUOUT[7:0];
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wire zero = ~|ALUOUT[15:0];
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wire zero = ~|ALUOUT[15:0];
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wire overflow8 = (SUMOP1[7] & SUMOP2[7] & !SUMOUT[7]) | (!SUMOP1[7] & !SUMOP2[7] & SUMOUT[7]);
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wire overflow8 = (SUMOP1[7] & SUMOP2[7] & !SUMOUT[7]) | (!SUMOP1[7] & !SUMOP2[7] & SUMOUT[7]);
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wire overflow = (SUMOP1[15] & SUMOP2[15] & !SUMOUT[15]) | (!SUMOP1[15] & !SUMOP2[15] & SUMOUT[15]);
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wire overflow = (SUMOP1[15] & SUMOP2[15] & !SUMOUT[15]) | (!SUMOP1[15] & !SUMOP2[15] & SUMOUT[15]);
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wire LO9 = RA[3:0] > 9;
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wire LONIBBLE = (RA[3:0] > 4'h9) || FIN[4];
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wire LONIBBLE = LO9 | FIN[4];
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wire HINIBBLE = (RA[7:0] > 8'h99) || FIN[0];
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wire HINIBBLE = (RA[7:4] > 8 && LO9) | FIN[0];
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// ADDER
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// ADDER
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assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
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assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
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assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
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assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
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assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
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assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
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| Line 205... |
Line 205... |
ALUOUT = SUMOUT;
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ALUOUT = SUMOUT;
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FOUT[0] = FIN[0];
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FOUT[0] = FIN[0];
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end
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end
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5'b01100, 5'b01101: begin // DAA, DAS
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5'b01100, 5'b01101: begin // DAA, DAS
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ALUOUT = SUMOUT;
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ALUOUT = SUMOUT;
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FOUT[0] = HINIBBLE ? 1'b1 : FIN[0];
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FOUT[0] = HINIBBLE;
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FOUT[4] = LONIBBLE ? 1'b1 : FIN[4];
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FOUT[4] = LONIBBLE;
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end
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end
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5'b01110, 5'b01111: begin // AAA, AAS
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5'b01110, 5'b01111: begin // AAA, AAS
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ALUOUT = {SUMOUT[15:8], 4'b0000, SUMOUT[3:0]};
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ALUOUT = {SUMOUT[15:8], 4'b0000, SUMOUT[3:0]};
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FOUT[0] = LONIBBLE;
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FOUT[0] = LONIBBLE;
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FOUT[4] = LONIBBLE;
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FOUT[4] = LONIBBLE;
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