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// Author: Nicolae Dumitrache
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// Author: Nicolae Dumitrache
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// e-mail: ndumitrache@opencores.org
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// e-mail: ndumitrache@opencores.org
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//
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//
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2011 Nicolae Dumitrache
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// Copyright (C) 2012 Nicolae Dumitrache
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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// Additional Comments:
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// Additional Comments:
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//
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//
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// Description: Next186 Bus Interface Unit, 32bit width SRAM, double CPU frequency (2T), delayed read (1T)
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// - Links the CPU with a 32bit static synchronous RAM (or cache)
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//
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// - Able to address up to 1MB
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// The CPU is able to execute (up to) one instrusction/clock with sepparate data and instruction buses.
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// - 16byte instruction queue
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// This particular bus interface links the CPU with a 32bit width memory bus and it is able to address up to 1MB.
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// - Works at 2 X CPU frequency (80Mhz on Spartan3AN), requiring minimum 2T for an instruction.
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// It have a 16byte instruction queue, and works at up to 80Mhz, allowing the CPU to execute an instruction at 2T. It is possible
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// - The 32bit data bus and the double CPU clock allows the instruction queue to be almost always full, avoiding the CPU starving.
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// to implement a BIU with sepparate data/instruction buses, which will run at the same frequency as the CPU, but it requires more resources.
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//
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// The 32bit data bus width and the double BIU clock allows the instruction queue to be almost always full, avoiding the CPU starving.
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// The data un-alignement penalties are required only when data words crosses the 4byte boundaries.
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// The data un-alignement penalties are required only when data words crosses the 4byte boundaries.
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// How to compute each instruction duration, in clock cycles (please note that it is specific to this particular BIU implementation):
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//
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// How to compute each instruction duration, in clock cycles (for this particular BIU implementation!):
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//
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//
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// 1 - From the Next186_features.doc see for each instruction how many T states are required (you will notice they are always
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// 1 - From the Next186_features.doc see for each instruction how many T states are required (you will notice they are always
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// less or equal than 486 and much less than the original 80186
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// less or equal than 486 and much less than the original 80186
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// 2 - multiply this number by 2 - the BIU works at double ALU frequency because it needs to multiplex the data and instructions,
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// 2 - Multiply this number by 2 - the BIU works at double ALU frequency because it needs to multiplex the data and instructions,
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// in order to keep the ALU permanently feed with instructions. The 16bit queue acts like a flexible instruction buffer.
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// in order to keep the ALU permanently feed with instructions. The 16bit queue acts like a flexible instruction buffer.
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// 3 - add penalties, as follows:
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// 3 - Add penalties, as follows:
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// +1T for each memory read - because of the synchronous SRAM which need this extra cycle to deliver the data
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// +1T for each memory read - because of the synchronous SRAM which need this extra cycle to deliver the data
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// +2T for each jump - required to flush and re-fill the instruction queue
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// +2T for each jump - required to flush and re-fill the instruction queue
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// +1T for each 16bit(word) read/write which overlaps the 4byte boundary - specific to 32bit bus width
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// +1T for each 16bit(word) read/write which overlaps the 4byte boundary - specific to 32bit bus width
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// +1T if the jump is made at an address with the latest 2bits 11 - specific to 32bit bus width
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// +1T if the jump is made at an address with the latest 2bits 11 - specific to 32bit bus width
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// +1T when the instruction queue empties - this case appears very rare, when a lot of 5-6 bytes memory write
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// +1T when the instruction queue empties - this case appears very rare, when a lot of 5-6 bytes memory write instructions are executed in direct sequence
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// instructions are executed one after the other
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//
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// Some examples:
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// Some examples:
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// - the instruction "inc word ptr [1]" will require 5T (2x2T inc M + 1T read)
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// - "lea ax,[bx+si+1234]" requires 2T
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// - the instruction "inc word ptr [3]" will require 7T (2x2T inc M + 1T read + 1T unaligned read + 1T unaligned write)
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// - "add ax, 2345" requires 2T
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// - the instruction "imul ax,bx,234" will require 4T (2x2T imul)
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// - "xchg ax, bx" requires 4T
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// - the instruction "loop <address = 1>" will require 4T (2x1T loop + 2T flush)
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// - "inc word ptr [1]" requires 5T (2x2T inc M + 1T read)
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// - the instruction "loop <address = 3>" will require 5T (2x1T loop + 2T flush + 1T unaligned jump)
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// - "inc word ptr [3]" requires 7T (2x2T inc M + 1T read + 1T unaligned read + 1T unaligned write)
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// - the instruction "call <address = 0>" will require 4T (2x1T call near + 2T flush
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// - "imul ax,bx,234" requires 4T (2x2T imul)
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// - the instruction "ret <address = 0>" will require 5T (2x2T ret + 1T read penalty)
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// - "loop address != 3(mod 4)" requires 4T (2x1T loop + 2T flush)
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// - "loop address == 3(mod 4)" requires 5T (2x1T loop + 2T flush + 1T unaligned jump)
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// - "call address 0" requires 4T (2x1T call near + 2T flush
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// - "ret address 0" requires 5T (2x2T ret + 1T read penalty)
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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