| Line 52... |
Line 52... |
// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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//
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//
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 03Apr2013 - fix RET n alignment bug
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// 04Apr2013 - fix TRAP interrupt acknowledge
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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|
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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| Line 178... |
Line 180... |
wire QSGN = (WORD ? DX[15] : AX[15]) & IDIV;
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wire QSGN = (WORD ? DX[15] : AX[15]) & IDIV;
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// interrupts
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// interrupts
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wire SAMPLEINT = ~(WE[2] & RASEL[1:0] == 2'b10) & ~status[2] & ~status[4] & ~status[5]; // not load SS, no prefix
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wire SAMPLEINT = ~(WE[2] & RASEL[1:0] == 2'b10) & ~status[2] & ~status[4] & ~status[5]; // not load SS, no prefix
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wire NMIACK = SNMI & ~FNMI; // NMI acknowledged
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wire NMIACK = SNMI & ~FNMI; // NMI acknowledged
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wire INTRACK = FLAGS[9] & (~WE[4] | FIN[9]) & SINTR; // INTR acknowledged (IF and not CLI in progress)
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wire INTRACK = FLAGS[9] & (~WE[4] | FIN[9]) & SINTR; // INTR acknowledged (IF and not CLI in progress)
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wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK)) | (~WE[2] & ~HALT & FLAGS[8]); // interrupt acknowledged
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wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK | (~HALT & FLAGS[8]))); // interrupt acknowledged (fixed 04Apr2013)
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reg CMPS; // early EQ test for CMPS
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reg CMPS; // early EQ test for CMPS
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reg SCAS; // early EQ test for SCAS
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reg SCAS; // early EQ test for SCAS
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|
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Next186_Regs REGS (
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Next186_Regs REGS (
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.RASEL(RASEL),
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.RASEL(RASEL),
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| Line 339... |
Line 341... |
default: ISIZEI = 5;
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default: ISIZEI = 5;
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endcase
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endcase
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end
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end
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always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
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always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
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WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT) begin
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WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT, IDIV) begin
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WORD = FETCH[0][0];
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WORD = FETCH[0][0];
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BASEL = FETCH[0][1] | &MOD;
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BASEL = FETCH[0][1] | &MOD;
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RASEL = FETCH[0][1] ? REG : RM; // destination
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RASEL = FETCH[0][1] ? REG : RM; // destination
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BBSEL = {1'b0, !FETCH[0][1] | &MOD};
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BBSEL = {1'b0, !FETCH[0][1] | &MOD};
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RBSEL = FETCH[0][1] ? RM : REG; // source
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RBSEL = FETCH[0][1] ? RM : REG; // source
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| Line 1285... |
Line 1287... |
end
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end
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endcase
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endcase
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end
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end
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// -------------------------------- ret near --------------------------------
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// -------------------------------- ret near --------------------------------
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41: begin
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41: begin
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WORD = 1'b1; // fix RET n alignment bug - 03Apr2013
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ISIZE = FETCH[0][0] ? 1 : 3;
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ISIZE = FETCH[0][0] ? 1 : 3;
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IFETCH = STAGE[0];
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IFETCH = STAGE[0];
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ALUOP = 31; // PASS B
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ALUOP = 31; // PASS B
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if(!STAGE[0]) begin // stage1, pop TMP16
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if(!STAGE[0]) begin // stage1, pop TMP16
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RSSEL = 2'b10; // SS
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RSSEL = 2'b10; // SS
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| Line 1304... |
Line 1307... |
MREQ = 1'b0;
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MREQ = 1'b0;
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end
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end
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end
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end
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// -------------------------------- ret far --------------------------------
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// -------------------------------- ret far --------------------------------
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42: begin
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42: begin
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WORD = 1'b1; // fix RET n alignment bug - 03Apr2013
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ALUOP = 31; // PASS B
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ALUOP = 31; // PASS B
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RSSEL = 2'b10; // SS
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RSSEL = 2'b10; // SS
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IFETCH = STAGE[1];
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IFETCH = STAGE[1];
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DISEL = 2'b00; // DIN
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DISEL = 2'b00; // DIN
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case(STAGE[1:0])
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case(STAGE[1:0])
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