URL
https://opencores.org/ocsvn/next186/next186/trunk
[/] [next186/] [trunk/] [Next186_CPU.v] - Diff between revs 5 and 7
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 5 |
Rev 7 |
| Line 49... |
Line 49... |
// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by
|
// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by
|
// a dedicated bus interface unit (BIU).
|
// a dedicated bus interface unit (BIU).
|
// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
|
// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
|
// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
|
// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
|
//
|
//
|
// 16May2012 - fixed CMPS/SCAS bug when interrupted on the <equal> item
|
// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
|
///////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
module Next186_CPU(
|
module Next186_CPU(
|
output [19:0] ADDR,
|
output [19:0] ADDR,
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.