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//
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//
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//typedef struct {
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//typedef struct {
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//bit [1] com;
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//bit [1] com;
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//bit [15:0] dat;
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//bit [15:0] dat;
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//} CDT_port;
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//} CDT_port;
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//
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//module Cell_Dyna_Tree ( clk, glob_com, stageGlb, is_input, in_prev, in_next, out );
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module Dyna_Tree ( clk, glob_com, dataIn, dataOut );
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//
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//parameter HBIT= 15;
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parameter HBIT= 7;
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//
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parameter TREE_LEVEL= 4;
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//
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//input clk;
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input clk;
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//input glob_com;
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input [1:0] glob_com;
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//
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//input stageGlb[3:0];
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input [HBIT:0] dataIn;
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//input candidateActive[3:0];
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output [HBIT:0] dataOut;
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//
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//input parentPtr[3:0];
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wire [HBIT:0] toLeft;
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//input [HBIT:0] pntInQuestMsg [3:0];
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wire [HBIT:0] toRight;
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//input [HBIT:0] cldInQuestMsg [3:0];
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wire [HBIT:0] fromLeft;
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//output active = |parentPtr;
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wire [HBIT:0] fromRight;
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//output [HBIT:0] message;
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//
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Cell_DT_Inner #( HBIT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut, toLeft, toRight );
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//output bit leftPtr [3:0];
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//output bit rightPtr[3:0];
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generate
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//
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if ( TREE_LEVEL >0 )
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//wire leftRq; // have left subtree
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begin
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//wire rightRq; // have right subtree
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Dyna_Tree #( HBIT, TREE_LEVEL-1 ) leftSubTree ( clk, glob_com, toLeft, fromLeft );
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//
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Dyna_Tree #( HBIT, TREE_LEVEL-1 ) rightSubTree ( clk, glob_com, toRight, fromRight );
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////wire parentMsg= pntInQuestMsg[];
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end
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//
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else
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//Cell_DT_Inner #( HBIT ) inner ( clk, glob_com, parentMsg, leftMsg, rightMsg, message );
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begin
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//
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assign fromLeft =1;
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//always@(posedge clk )
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assign fromRight=1;
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//begin
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end
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// if ( leftRq )
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endgenerate
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// begin
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// if ( leftPtr==0 ) // new child required
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// begin
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endmodule
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// if ( stageGlb & ~candidateActive )
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// begin
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// leftPtr<= stageGlb;
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typedef enum { VMS_NOMESSAGE=0,
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// end
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VMS_WRITE,
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// end
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VMS_READ
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// end
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} VMeta;
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// else
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// begin
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module Cell_DT_Inner ( clk, glob_com, fromParent, fromLeft, fromRight, toParent, toLeft, toRight );
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// leftPtr<= 0;
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parameter HBIT= 7;
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// end
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// if (~hold)
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input clk;
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// begin
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input [1:0] glob_com;
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// higher <= ( cand_h > cand_l ) ? cand_h : cand_l;
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// lower <= ( cand_h > cand_l ) ? cand_l : cand_h;
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input [HBIT:0] fromParent;
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// end
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input [HBIT:0] fromLeft;
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//end
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input [HBIT:0] fromRight;
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//endmodule
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//
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output [HBIT:0] toParent;
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//
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output [HBIT:0] toLeft;
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//module Cell_DT_Inner ( clk, glob_com, parentMsg, leftMsg, rightMsg, message );
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output [HBIT:0] toRight;
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//parameter HBIT= 15;
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//
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reg [HBIT:0] value;
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//input clk;
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reg [HBIT:0] message;
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//input [1:0]glob_com;
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VMeta state;
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//
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//input [HBIT:0] parentMsg;
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assign toParent= value + message;
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//input [HBIT:0] leftMsg;
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assign toLeft= message;
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//input [HBIT:0] rightMsg;
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assign toRight= value;
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//output [HBIT:0] message;
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//
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always@(posedge clk )
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//reg [HBIT:0] store;
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begin
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//reg [HBIT:0] tmp;
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case( state )
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//
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VMS_NOMESSAGE: ;
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//always@(posedge clk )
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VMS_WRITE:
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//begin
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begin
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// case( glob_com )
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value <= fromParent +1;
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// 2'h0: ;
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message <= fromParent;
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// 2'h1: ;
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end
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// 2'h2:
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VMS_READ:
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// begin
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begin
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// higher <= ( cand_h > cand_l ) ? cand_h : cand_l;
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value <= fromLeft;
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// lower <= ( cand_h > cand_l ) ? cand_l : cand_h;
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message <= fromRight;
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// end
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end
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// 2'h3: ;
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2'h3: ;
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// endcase
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default: ;
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//end
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endcase
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//
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state <= VMeta'(glob_com);
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//endmodule
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end
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//
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//
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endmodule
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//
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