Line 52... |
Line 52... |
.tumblers( iColor_SW ), .endFrame(endFrame3),
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.tumblers( iColor_SW ), .endFrame(endFrame3),
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.dbg_val(_)
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.dbg_val(_)
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);
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);
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wire [7:0] mp_test_out;
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wire [7:0] mp_test_out;
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assign dbg_val= iColor_SW[7] ? dbg_val_i:chrono;
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assign dbg_val= iColor_SW[7] ? dbg_val_i:chrono;
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always@(posedge iVGA_CLK or negedge iRST_n)
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always@(posedge iVGA_CLK or negedge iRST_n)
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Line 138... |
Line 139... |
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// tumblers[4] ? increasing order : decreasing order
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// tumblers[4] ? increasing order : decreasing order
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wire [HBIT:0] _data_in= tumblers[4] ? -1-data_in : data_in;
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wire [HBIT:0] _data_in= tumblers[4] ? -1-data_in : data_in;
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Sorting_Tree #(HBIT,R_SZ) ctree ( clk, ~cell_clk, is_input, _data_in, _d_out_3 );
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Sorting_Tree #(HBIT,R_SZ) ctree ( clk, ~cell_clk, is_input, _data_in, _d_out_3 );
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wire [HBIT:0] d_out_3 = tumblers[4] ? -1-_d_out_3 : _d_out_3;
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wire [HBIT:0] d_out_3 = tumblers[4] ? -1-_d_out_3 : _d_out_3;
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Sorting_Tree #(HBIT,R_SZ) cstack ( clk, ~cell_clk, is_input, _data_in, _data_out );
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Sorting_Stack #(HBIT,R_SZ) cstack ( clk, ~cell_clk, is_input, _data_in, _data_out );
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wire [HBIT:0] data_out= tumblers[4] ? -1-_data_out : _data_out;
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wire [HBIT:0] data_out= tumblers[4] ? -1-_data_out : _data_out;
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reg [11:0]count;
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reg [11:0]count;
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wire is_input= !cell_rst && count<R_SZ;
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wire is_input= !cell_rst && count<R_SZ;
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wire is_enable=!cell_rst && count<R_SZ*2;
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wire is_enable=!cell_rst && count<R_SZ*2;
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