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Staus: TLDR Version: Simulations are working
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Staus: TLDR Version: Simulations are working
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This code was written a long time ago and I've learned much more about verilog and project organization
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This code was written a long time ago and I've learned much more about verilog and project organization
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since then. It has been proven in a Virtex 6 FPGA reading and writing to/from four Sata 2 hard drives at
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since then. It has been proven in a Virtex 6 FPGA reading and writing to/from four Sata 2 hard drives at
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the same time. There were some issues found when the internal buffers inside the hard drives began to
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fill up requiring a lot of starting and stopping of this stack. It lead to some dropped data. There was
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a horrible fix for it in the sata_link_write.v involving a small buffer. This made if very difficult to
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debug because the stack wouldn't allow me to read the non-scrambled data within the logic analyzer.
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There should be a more elegant solution to it.
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Most of the license is MIT but some of the licenses are GPL
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Most of the license is MIT but some of the licenses are GPL
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TODO: Fix Link layer... there is a small FIFO in there that is used to handle all starting and stopping
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TODO: Fix Link layer... there is a small FIFO in there that is used to handle all starting and stopping
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of the read, it's a work around and needs to be fixed
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of the read, it's a work around and needs to be fixed
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