| Line 56... |
Line 56... |
);
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);
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localparam FIFO_DEPTH = (1 << ADDRESS_WIDTH);
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localparam FIFO_DEPTH = (1 << ADDRESS_WIDTH);
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//Local Registers/Wires
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//Local Registers/Wires
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assign write_fifo_size = FIFO_DEPTH;
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//Write Side
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//Write Side
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wire ppfifo_ready; // The write side only needs to
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wire ppfifo_ready; // The write side only needs to
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// know were ready if we don't
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// know were ready if we don't
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// write anything read won't start
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// write anything read won't start
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| Line 84... |
Line 83... |
reg w_empty[1:0];
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reg w_empty[1:0];
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reg w_reset; //write side reset
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reg w_reset; //write side reset
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reg [4:0] w_reset_timeout;
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reg [4:0] w_reset_timeout;
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wire ready;
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wire ready;
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//assign r_wselect = (write_activate == 2'b00) ? 1'b0 :
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// (write_activate == 2'b01) ? 1'b0 :
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// (write_activate == 2'b10) ? 1'b1 :
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// reset ? 1'b0 :
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// r_wselect;
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// //I know this can be shortened down but it's more
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// //readible thi way
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assign addr_in = {r_wselect, write_address};
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//assign write_enable = (write_activate > 0) && write_strobe;
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assign ppfifo_ready = !(w_reset || r_reset);
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assign ready = ppfifo_ready;
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//assign wcc_tie_select = (wcc_read_ready == 2'b00) ? 1'b0 :
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// (wcc_read_ready == 2'b01) ? 1'b0 :
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// (wcc_read_ready == 2'b10) ? 1'b1 :
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// wcc_tie_select;
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// If the first FIFO is ready,
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// then both FIFOs are ready then
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// keep the first FIFO
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//Read Side
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//Read Side
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wire [ADDRESS_WIDTH: 0] addr_out; //Actual address to the BRAM
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wire [ADDRESS_WIDTH: 0] addr_out; //Actual address to the BRAM
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reg r_reset;
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reg r_reset;
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reg [4:0] r_reset_timeout;
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reg [4:0] r_reset_timeout;
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| Line 138... |
Line 116... |
reg r_pre_read_wait;//Wait an extra cycle so the registered data has a chance to set
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reg r_pre_read_wait;//Wait an extra cycle so the registered data has a chance to set
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//the data to be registered
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//the data to be registered
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wire [DATA_WIDTH - 1: 0] w_read_data; //data from the read FIFO
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wire [DATA_WIDTH - 1: 0] w_read_data; //data from the read FIFO
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reg [DATA_WIDTH - 1: 0] r_read_data; //data from the read FIFO
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reg [DATA_WIDTH - 1: 0] r_read_data; //data from the read FIFO
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//assign r_wselect = (write_activate == 2'b00) ? 1'b0 :
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// (write_activate == 2'b01) ? 1'b0 :
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// (write_activate == 2'b10) ? 1'b1 :
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// reset ? 1'b0 :
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// r_wselect;
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// //I know this can be shortened down but it's more
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// //readible thi way
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assign write_fifo_size = FIFO_DEPTH;
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assign addr_in = {r_wselect, write_address};
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//assign write_enable = (write_activate > 0) && write_strobe;
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assign ppfifo_ready = !(w_reset || r_reset);
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assign ready = ppfifo_ready;
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//assign wcc_tie_select = (wcc_read_ready == 2'b00) ? 1'b0 :
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// (wcc_read_ready == 2'b01) ? 1'b0 :
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// (wcc_read_ready == 2'b10) ? 1'b1 :
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// wcc_tie_select;
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// If the first FIFO is ready,
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// then both FIFOs are ready then
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// keep the first FIFO
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assign addr_out = {r_rselect, r_address};
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assign addr_out = {r_rselect, r_address};
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//Debug
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//Debug
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wire [23:0] debug_f0_w_count;
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//wire [23:0] debug_f0_w_count;
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wire [23:0] debug_f1_w_count;
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//wire [23:0] debug_f1_w_count;
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wire [23:0] debug_f0_r_size;
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//wire [23:0] debug_f0_r_size;
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wire [23:0] debug_f1_r_size;
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//wire [23:0] debug_f1_r_size;
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//wire [23:0] debug_f0_r_count;
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//wire [23:0] debug_f0_r_count;
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//wire [23:0] debug_f1_r_count;
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//wire [23:0] debug_f1_r_count;
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assign debug_f0_w_count = w_count[0];
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//assign debug_f0_w_count = w_count[0];
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assign debug_f1_w_count = w_count[1];
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//assign debug_f1_w_count = w_count[1];
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assign debug_f0_r_size = r_size[0];
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//assign debug_f0_r_size = r_size[0];
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assign debug_f1_r_size = r_size[1];
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//assign debug_f1_r_size = r_size[1];
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assign inactive = (w_count[0] == 0) &&
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assign inactive = (w_count[0] == 0) &&
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(w_count[1] == 0) &&
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(w_count[1] == 0) &&
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(write_ready == 2'b11) &&
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(write_ready == 2'b11) &&
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(!write_strobe);
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(!write_strobe);
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| Line 289... |
Line 292... |
if (reset) begin
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if (reset) begin
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w_reset <= 1;
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w_reset <= 1;
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w_reset_timeout <= 0;
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w_reset_timeout <= 0;
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end
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end
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else begin
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else begin
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if (w_reset && (w_reset_timeout < 4'h4)) begin
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if (w_reset && (w_reset_timeout < 5'h4)) begin
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w_reset_timeout <= w_reset_timeout + 1;
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w_reset_timeout <= w_reset_timeout + 5'h1;
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end
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end
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else begin
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else begin
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w_reset <= 0;
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w_reset <= 0;
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end
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end
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end
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end
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| Line 304... |
Line 307... |
if (reset) begin
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if (reset) begin
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r_reset <= 1;
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r_reset <= 1;
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r_reset_timeout <= 0;
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r_reset_timeout <= 0;
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end
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end
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else begin
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else begin
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if (r_reset && (r_reset_timeout < 4'h4)) begin
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if (r_reset && (r_reset_timeout < 5'h4)) begin
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r_reset_timeout <= r_reset_timeout + 1;
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r_reset_timeout <= r_reset_timeout + 5'h1;
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end
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end
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else begin
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else begin
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r_reset <= 0;
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r_reset <= 0;
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end
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end
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end
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end
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