| Line 34... |
Line 34... |
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input last_prim,
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input last_prim,
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input [31:0] ll_tx_din,
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input [31:0] ll_tx_din,
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input ll_tx_isk,
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input ll_tx_is_k,
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output [31:0] cont_tx_dout,
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output [31:0] cont_tx_dout,
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output cont_tx_isk,
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output cont_tx_is_k,
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input [31:0] rx_din,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input [3:0] rx_is_k,
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output detect_sync,
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output detect_sync,
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output detect_r_rdy,
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output detect_r_rdy,
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output detect_r_ip,
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output detect_r_ip,
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output detect_r_err,
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output detect_r_err,
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| Line 116... |
Line 116... |
.din (ll_tx_din ),
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.din (ll_tx_din ),
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.dout (scram_dout )
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.dout (scram_dout )
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);
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);
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//Asynchronous Logic
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//Asynchronous Logic
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assign detect_sync = ((rx_isk[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
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assign detect_sync = ((rx_is_k[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
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assign detect_r_rdy = ((rx_isk[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
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assign detect_r_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
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assign detect_r_ip = ((rx_isk[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
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assign detect_r_ip = ((rx_is_k[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
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assign detect_r_err = ((rx_isk[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
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assign detect_r_err = ((rx_is_k[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
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assign detect_r_ok = ((rx_isk[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
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assign detect_r_ok = ((rx_is_k[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
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assign detect_x_rdy = ((rx_isk[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
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assign detect_x_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
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assign detect_sof = (rx_isk[0]) && (rx_din == `PRIM_SOF );
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assign detect_sof = (rx_is_k[0]) && (rx_din == `PRIM_SOF );
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assign detect_eof = (rx_isk[0]) && (rx_din == `PRIM_EOF );
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assign detect_eof = (rx_is_k[0]) && (rx_din == `PRIM_EOF );
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assign detect_wtrm = ((rx_isk[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
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assign detect_wtrm = ((rx_is_k[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
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assign detect_cont = (rx_isk[0]) && (rx_din == `PRIM_CONT );
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assign detect_cont = (rx_is_k[0]) && (rx_din == `PRIM_CONT );
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assign detect_hold = ((rx_isk[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
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assign detect_hold = ((rx_is_k[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
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assign detect_holda = ((rx_isk[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
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assign detect_holda = ((rx_is_k[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
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assign detect_preq_s = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
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assign detect_preq_s = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
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assign detect_preq_p = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
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assign detect_preq_p = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
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assign detect_align = (rx_isk[0]) && (rx_din == `PRIM_ALIGN );
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assign detect_align = (rx_is_k[0]) && (rx_din == `PRIM_ALIGN );
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assign detect_xrdy_xrdy = ((((rx_isk[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_isk && (ll_tx_din == `PRIM_X_RDY));
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assign detect_xrdy_xrdy = ((((rx_is_k[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_is_k && (ll_tx_din == `PRIM_X_RDY));
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assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
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assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
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((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_din : //if the prev != curr (exit)
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((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_din : //if the prev != curr (exit)
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(last_prim) ? ll_tx_din:
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(last_prim) ? ll_tx_din:
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(tx_cont_enable) ? //if the cont is enabled
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(tx_cont_enable) ? //if the cont is enabled
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send_cont ? `PRIM_CONT : //need to first send the cont
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send_cont ? `PRIM_CONT : //need to first send the cont
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scram_dout : //send the junk
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scram_dout : //send the junk
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ll_tx_din; //tx cont is not enabled
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ll_tx_din; //tx cont is not enabled
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assign cont_tx_isk = (!xmit_cont_en) ? ll_tx_isk :
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assign cont_tx_is_k = (!xmit_cont_en) ? ll_tx_is_k :
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((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_isk ://if the prev != curr (exit)
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((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_is_k ://if the prev != curr (exit)
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(last_prim) ?ll_tx_isk:
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(last_prim) ?ll_tx_is_k:
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(tx_cont_enable) ? //if the cont is enabled
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(tx_cont_enable) ? //if the cont is enabled
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send_cont ? 1 : //need to first send the cont
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send_cont ? 1'b1 : //need to first send the cont
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0 : //send the junk
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1'b0 : //send the junk
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ll_tx_isk; //tx cont is not enabled
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ll_tx_is_k; //tx cont is not enabled
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assign scram_en = tx_cont_enable;
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assign scram_en = tx_cont_enable;
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//Synchronous logic
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//Synchronous logic
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//Cont detect
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//Cont detect
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| Line 186... |
Line 186... |
x_rdy_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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end
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end
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else begin
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else begin
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if (!detect_align) begin
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if (!detect_align) begin
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if (rx_isk) begin
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if (rx_is_k) begin
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if (rx_din == `PRIM_CONT) begin
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if (rx_din == `PRIM_CONT) begin
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cont_detect <= 1;
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cont_detect <= 1;
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end
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end
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else if (prev_prim == rx_din) begin
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else if (prev_prim == rx_din) begin
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case (prev_prim)
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case (prev_prim)
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| Line 273... |
Line 273... |
wtrm_cont_ready <= 0;
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wtrm_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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end
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end
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end
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end
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if (!rx_isk[0] && !cont_detect) begin
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if (!rx_is_k[0] && !cont_detect) begin
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cont_detect <= 0;
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cont_detect <= 0;
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hold_cont_ready <= 0;
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hold_cont_ready <= 0;
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holda_cont_ready <= 0;
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holda_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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| Line 305... |
Line 305... |
else begin
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else begin
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if (phy_ready) begin
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if (phy_ready) begin
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send_cont <= 0;
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send_cont <= 0;
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if (ll_tx_isk) begin
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if (ll_tx_is_k) begin
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//reset everything because the previous primative is not equal to the current one
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//reset everything because the previous primative is not equal to the current one
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if (tx_prev_prim != ll_tx_din) begin
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if (tx_prev_prim != ll_tx_din) begin
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send_cont <= 0;
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send_cont <= 0;
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tx_cont_sent <= 0;
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tx_cont_sent <= 0;
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