| Line 40... |
Line 40... |
output write_ready,
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output write_ready,
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input platform_ready,
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input platform_ready,
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//XXX: I probably need some feedback to indicate that there is room to write
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//XXX: I probably need some feedback to indicate that there is room to write
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output [31:0] tx_dout,
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output [31:0] tx_dout,
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output tx_isk,
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output tx_is_k,
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input [31:0] rx_din,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input [3:0] rx_is_k,
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input write_start,
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input write_start,
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output write_strobe,
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output write_strobe,
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input [31:0] write_data,
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input [31:0] write_data,
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input [31:0] write_size,
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input [23:0] write_size,
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input write_hold,
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input write_hold,
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output write_finished,
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output write_finished,
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input write_abort,
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input write_abort,
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output read_start,
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output read_start,
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| Line 120... |
Line 120... |
reg send_pmnack;
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reg send_pmnack;
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wire sli_idle;
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wire sli_idle;
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wire [31:0] sli_tx_dout;
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wire [31:0] sli_tx_dout;
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wire sli_tx_isk;
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wire sli_tx_is_k;
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reg write_en;
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reg write_en;
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wire write_idle;
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wire write_idle;
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wire [31:0] slw_tx_dout;
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wire [31:0] slw_tx_dout;
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wire slw_tx_isk;
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wire slw_tx_is_k;
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reg read_en;
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reg read_en;
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wire read_idle;
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wire read_idle;
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wire [31:0] slr_tx_dout;
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wire [31:0] slr_tx_dout;
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wire slr_tx_isk;
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wire slr_tx_is_k;
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wire [31:0] ll_tx_dout;
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wire [31:0] ll_tx_dout;
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wire ll_tx_isk;
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wire ll_tx_is_k;
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wire last_prim;
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wire last_prim;
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//Submodules
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//Submodules
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| Line 153... |
Line 153... |
.phy_ready (phy_ready ),
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.phy_ready (phy_ready ),
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.xmit_cont_en (prim_scrambler_en ),
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.xmit_cont_en (prim_scrambler_en ),
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.last_prim (last_prim ),
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.last_prim (last_prim ),
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|
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.rx_din (rx_din ),
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.rx_din (rx_din ),
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.rx_isk (rx_isk ),
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.rx_is_k (rx_is_k ),
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|
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.ll_tx_din (ll_tx_dout ),
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.ll_tx_din (ll_tx_dout ),
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.ll_tx_isk (ll_tx_isk ),
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.ll_tx_is_k (ll_tx_is_k ),
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|
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.cont_tx_dout (tx_dout ),
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.cont_tx_dout (tx_dout ),
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.cont_tx_isk (tx_isk ),
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.cont_tx_is_k (tx_is_k ),
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|
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.detect_sync (detect_sync ),
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.detect_sync (detect_sync ),
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.detect_r_rdy (detect_r_rdy ),
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.detect_r_rdy (detect_r_rdy ),
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.detect_r_ip (detect_r_ip ),
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.detect_r_ip (detect_r_ip ),
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.detect_r_err (detect_r_err ),
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.detect_r_err (detect_r_err ),
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| Line 214... |
Line 214... |
.last_prim (last_prim ),
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.last_prim (last_prim ),
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.send_crc (send_crc ),
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.send_crc (send_crc ),
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.post_align_write (post_align_write ),
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.post_align_write (post_align_write ),
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|
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.tx_dout (slw_tx_dout ),
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.tx_dout (slw_tx_dout ),
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.tx_isk (slw_tx_isk ),
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.tx_is_k (slw_tx_is_k ),
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.rx_din (rx_din ),
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.rx_din (rx_din ),
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.rx_isk (rx_isk ),
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.rx_is_k (rx_is_k ),
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|
|
.xmit_error (xmit_error ),
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.xmit_error (xmit_error ),
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.wsize_z_error (wsize_z_error ),
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.wsize_z_error (wsize_z_error ),
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|
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.data_scrambler_en (data_scrambler_en ),
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.data_scrambler_en (data_scrambler_en ),
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| Line 253... |
Line 253... |
.detect_holda (detect_holda ),
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.detect_holda (detect_holda ),
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.detect_hold (detect_hold ),
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.detect_hold (detect_hold ),
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.detect_xrdy_xrdy (detect_xrdy_xrdy ),
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.detect_xrdy_xrdy (detect_xrdy_xrdy ),
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|
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.tx_dout (slr_tx_dout ),
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.tx_dout (slr_tx_dout ),
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.tx_isk (slr_tx_isk ),
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.tx_is_k (slr_tx_is_k ),
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.rx_din (rx_din ),
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.rx_din (rx_din ),
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.rx_isk (rx_isk ),
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.rx_is_k (rx_is_k ),
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|
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.read_ready (read_ready ),
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.read_ready (read_ready ),
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.read_strobe (read_strobe ),
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.read_strobe (read_strobe ),
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.read_data (read_data ),
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.read_data (read_data ),
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.read_start (read_start ),
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.read_start (read_start ),
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| Line 273... |
Line 273... |
.lax_r_state (lax_r_state )
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.lax_r_state (lax_r_state )
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);
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);
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|
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//Asynchronous logic
|
//Asynchronous logic
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assign ll_tx_dout = (!read_idle) ? slr_tx_dout : (!write_idle) ? slw_tx_dout : sli_tx_dout;
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assign ll_tx_dout = (!read_idle) ? slr_tx_dout : (!write_idle) ? slw_tx_dout : sli_tx_dout;
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assign ll_tx_isk = (!read_idle) ? slr_tx_isk : (!write_idle) ? slw_tx_isk : sli_tx_isk;
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assign ll_tx_is_k = (!read_idle) ? slr_tx_is_k : (!write_idle) ? slw_tx_is_k : sli_tx_is_k;
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assign sli_tx_dout = (send_pmnack) ? `PRIM_PMNACK :
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assign sli_tx_dout = (send_pmnack) ? `PRIM_PMNACK :
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(send_pmack) ? `PRIM_PMACK :
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(send_pmack) ? `PRIM_PMACK :
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`PRIM_SYNC;
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`PRIM_SYNC;
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assign sli_tx_isk = 1;
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assign sli_tx_is_k = 1;
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assign link_layer_ready = (state == IDLE) && read_idle && write_idle;
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assign link_layer_ready = (state == IDLE) && read_idle && write_idle;
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assign lax_i_state = state;
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assign lax_i_state = state;
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