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[/] [nysa_sata/] [trunk/] [rtl/] [link/] [sata_link_layer_write.v] - Diff between revs 2 and 3

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Line 22... Line 22... 
SOFTWARE.
 
SOFTWARE.
 
*/
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
//THERE APPEARS TO BE AN ERROR WHEN WRITING TO A HARDDRIVE, IT MANIFESTS AS A CRC ERROR
 
 
 
 
 
 
 
`include "sata_defines.v"
 
`include "sata_defines.v"
 
 
 
 
 
`define MIN_HOLDA_TIMEOUT 4
 
`define MIN_HOLDA_TIMEOUT 4
 
`define DHOLD_DELAY       8
 
`define DHOLD_DELAY       8
 
`define DHOLD_DELAY_EN    0
 
`define DHOLD_DELAY_EN    0
Line 56... Line 54... 
 
 
 
 
 
 
 
 
  output  reg         send_holda,
 
  output  reg         send_holda,
 
 
 
 
 
  output      [31:0]  tx_dout,
 
  output      [31:0]  tx_dout,
 
  output              tx_isk,
 
  output              tx_is_k,
 
 
 
 
 
  input       [31:0]  rx_din,
 
  input       [31:0]  rx_din,
 
  input       [3:0]   rx_isk,
 
  input       [3:0]   rx_is_k,
 
 
 
 
 
  input               write_start,
 
  input               write_start,
 
  output  reg         write_strobe,
 
  output  reg         write_strobe,
 
  input       [31:0]  write_data,
 
  input       [31:0]  write_data,
 
  input       [31:0]  write_size,  //maximum 2048
 
  input       [23:0]  write_size,  //maximum 2048
 
  input               write_hold,
 
  input               write_hold,
 
  output  reg         write_finished,
 
  output  reg         write_finished,
 
  output  reg         xmit_error,
 
  output  reg         xmit_error,
 
  output  reg         wsize_z_error,
 
  output  reg         wsize_z_error,
 
  input               write_abort,
 
  input               write_abort,
Line 92... Line 90... 
parameter           IDLE            = 4'h0;
 
parameter           IDLE            = 4'h0;
 
 
 
 
 
//fstate
 
//fstate
 
parameter           FIRST_DATA      = 4'h1;
 
parameter           FIRST_DATA      = 4'h1;
 
parameter           ENQUEUE         = 4'h2;
 
parameter           ENQUEUE         = 4'h2;
 
parameter           WRITE_CRC       = 4'h3;
 
parameter           LAST_DATA       = 4'h3;
 
parameter           WAIT            = 4'h4;
 
parameter           WRITE_CRC       = 4'h4;
 
 
 
parameter           WAIT            = 4'h5;
 
 
 
 
 
//state
 
//state
 
parameter           WRITE_START     = 4'h1;
 
parameter           WRITE_START     = 4'h1;
 
parameter           WRITE           = 4'h2;
 
parameter           WRITE           = 4'h2;
 
parameter           WRITE_END       = 4'h3;
 
parameter           WRITE_END       = 4'h3;
Line 133... Line 132... 
 
 
 
 
 
 
 
 
//CRC
 
//CRC
 
//XXX: Tie the CRC_EN to the read strobe
 
//XXX: Tie the CRC_EN to the read strobe
 
wire      [31:0]    crc_dout;
 
wire      [31:0]    crc_dout;
 
reg       [31:0]    crc_data;
 
 
 
 
 
 
 
//Scrambler
 
//Scrambler
 
reg                 scr_rst;
 
reg                 scr_rst;
 
reg                 scr_en;
 
reg                 scr_en;
 
reg       [31:0]    scr_din;
 
reg       [31:0]    scr_din;
Line 207... Line 205... 
                              (send_hold)   ? `PRIM_HOLD:
 
                              (send_hold)   ? `PRIM_HOLD:
 
                              (send_holda)  ? `PRIM_HOLDA:
 
                              (send_holda)  ? `PRIM_HOLDA:
 
                              (send_sync)   ? `PRIM_SYNC:
 
                              (send_sync)   ? `PRIM_SYNC:
 
                              bump_buffer[buffer_pos];
 
                              bump_buffer[buffer_pos];
 
 
 
 
 
assign              tx_isk  = ( send_x_rdy  ||
 
assign              tx_is_k = ( send_x_rdy  ||
 
                                send_sof    ||
 
                                send_sof    ||
 
                                send_eof    ||
 
                                send_eof    ||
 
                                send_wtrm   ||
 
                                send_wtrm   ||
 
                                send_cont   ||
 
                                send_cont   ||
 
                                send_hold   ||
 
                                send_hold   ||
Line 231... Line 229... 
assign              d3_buf                    = bump_buffer[3];
 
assign              d3_buf                    = bump_buffer[3];
 
assign              write_ready               = phy_ready && !send_holda;
 
assign              write_ready               = phy_ready && !send_holda;
 
 
 
 
 
 
 
 
 
//Synchronous Logic
 
//Synchronous Logic
 
//Incomming buffer (this is the buffer afte the scrambler and CRC)
 
//Incomming buffer (this is the buffer after the scrambler and CRC)
 
always @ (posedge clk) begin
 
always @ (posedge clk) begin
 
  if (rst) begin
 
  if (rst) begin
 
    fstate          <=  IDLE;
 
    fstate          <=  IDLE;
 
    data_size       <=  0;
 
    data_size       <=  0;
 
    in_data_addra   <=  0;
 
    in_data_addra   <=  0;
 
    scr_din         <=  0;
 
    scr_din         <=  0;
 
    scr_en          <=  0;
 
    scr_en          <=  0;
 
    scr_rst         <=  1;
 
    scr_rst         <=  1;
 
    wr_en           <=  0;
 
    wr_en           <=  0;
 
    write_strobe    <=  0;
 
    write_strobe    <=  0;
 
    crc_data        <=  0;
 
 
 
  end
 
  end
 
  else begin
 
  else begin
 
    //Strobes
 
    //Strobes
 
    scr_en          <=  0;
 
    scr_en          <=  0;
 
    wr_en           <=  0;
 
    wr_en           <=  0;
Line 265... Line 262... 
          scr_din         <=  0;
 
          scr_din         <=  0;
 
          fstate          <=  FIRST_DATA;
 
          fstate          <=  FIRST_DATA;
 
        end
 
        end
 
      end
 
      end
 
      FIRST_DATA: begin
 
      FIRST_DATA: begin
 
 
 
          //$display ("LLW: Data Size: %d", data_size);
 
          write_strobe    <=  1;
 
          write_strobe    <=  1;
 
          wr_en           <=  1;
 
          wr_en           <=  1;
 
          scr_en          <=  1;
 
          scr_en          <=  1;
 
          scr_din         <=  write_data;
 
          scr_din         <=  write_data;
 
          fstate          <=  ENQUEUE;
 
          fstate          <=  ENQUEUE;
 
      end
 
 
 
      ENQUEUE: begin
 
 
 
        if (data_size == 1) begin
 
        if (data_size == 1) begin
 
          in_data_addra   <=  in_data_addra + 1;
 
            fstate        <=  LAST_DATA;
 
          wr_en           <=  1;
 
 
 
          scr_en          <=  1;
 
 
 
          scr_din         <=  crc_dout;
 
 
 
          fstate          <=  WRITE_CRC;
 
 
 
        end
 
        end
 
        else begin
 
        else begin
 
          if (in_data_addra < data_size - 1) begin
 
            fstate        <=  ENQUEUE;
 
//          if (in_data_addra < data_size) begin
 
          end
 
            //Put all the data into the FIFO
 
      end
 
            write_strobe    <=  1;
 
      ENQUEUE: begin
 
 
 
        in_data_addra   <=  in_data_addra + 24'h1;
 
            wr_en           <=  1;
 
            wr_en           <=  1;
 
            scr_en          <=  1;
 
            scr_en          <=  1;
 
            in_data_addra   <=  in_data_addra + 1;
 
 
 
            scr_din         <=  write_data;
 
            scr_din         <=  write_data;
 
 
 
        //write_strobe    <=  1;
 
 
 
        if (in_data_addra < data_size - 2) begin
 
 
 
            write_strobe    <=  1;
 
          end
 
          end
 
          else begin
 
          else begin
 
            //put the CRC into the FIFO
 
            fstate      <=  LAST_DATA;
 
            //in_data_addra   <=  in_data_addra + 1;
 
        end
 
 
 
      end
 
 
 
      LAST_DATA: begin
 
 
 
        in_data_addra       <=  in_data_addra + 24'h1;
 
            wr_en           <=  1;
 
            wr_en           <=  1;
 
            scr_en          <=  1;
 
            scr_en          <=  1;
 
            in_data_addra   <=  in_data_addra + 1;
 
 
 
            scr_din         <=  crc_dout;
 
            scr_din         <=  crc_dout;
 
            fstate          <=  WRITE_CRC;
 
            fstate          <=  WRITE_CRC;
 
          end
 
          end
 
        end
 
 
 
      end
 
 
 
      WRITE_CRC: begin
 
      WRITE_CRC: begin
 
        fstate            <=  WAIT;
 
        fstate            <=  WAIT;
 
      end
 
      end
 
      WAIT: begin
 
      WAIT: begin
 
        scr_rst           <=  1;
 
        scr_rst           <=  1;
Line 336... Line 331... 
 
 
 
 
  end
 
  end
 
  else begin
 
  else begin
 
 
 
 
 
    if (dhold_delay_cnt < `DHOLD_DELAY) begin
 
    if (dhold_delay_cnt < `DHOLD_DELAY) begin
 
      dhold_delay_cnt <=  dhold_delay_cnt + 1;
 
      dhold_delay_cnt <=  dhold_delay_cnt + 4'h1;
 
    end
 
    end
 
    else begin
 
    else begin
 
      dhold_delay   <=  1;
 
      dhold_delay   <=  1;
 
    end
 
    end
 
 
 
 
Line 392... Line 387... 
    d_count         <=  0;
 
    d_count         <=  0;
 
    buffer_pos      <=  0;
 
    buffer_pos      <=  0;
 
 
 
 
 
  end
 
  end
 
  else begin
 
  else begin
 
 
 
//XXX: Remove Bump Buffer
 
    if ((state == WRITE_START) || ((state != IDLE) &&  (d_count != write_count))) begin
 
    if ((state == WRITE_START) || ((state != IDLE) &&  (d_count != write_count))) begin
 
      bump_buffer[3]  <=  bump_buffer[2];
 
      bump_buffer[3]  <=  bump_buffer[2];
 
      bump_buffer[2]  <=  bump_buffer[1];
 
      bump_buffer[2]  <=  bump_buffer[1];
 
      bump_buffer[1]  <=  bump_buffer[0];
 
      bump_buffer[1]  <=  bump_buffer[0];
 
      bump_buffer[0]  <=  rd_dout;
 
      bump_buffer[0]  <=  rd_dout;
 
      d_count         <=  write_count;
 
      d_count         <=  write_count;
 
    end
 
    end
 
 
 
//XXX: End Remove Bump Buffer
 
 
 
 
 
    //write_strobe    <=  0;
 
    //write_strobe    <=  0;
 
    write_finished  <=  0;
 
    write_finished  <=  0;
 
 
 
 
 
    xmit_error      <=  0;
 
    xmit_error      <=  0;
Line 416... Line 413... 
`else
 
`else
 
    prev_hold     <=  detect_hold;
 
    prev_hold     <=  detect_hold;
 
`endif
 
`endif
 
 
 
 
 
    if (min_holda_count < `MIN_HOLDA_TIMEOUT) begin
 
    if (min_holda_count < `MIN_HOLDA_TIMEOUT) begin
 
      min_holda_count <=  min_holda_count + 1;
 
      min_holda_count <=  min_holda_count + 4'h1;
 
    end
 
    end
 
 
 
 
 
    if (phy_ready) begin
 
    if (phy_ready) begin
 
      send_sync     <=  0;
 
      send_sync     <=  0;
 
      send_x_rdy    <=  0;
 
      send_x_rdy    <=  0;
Line 454... Line 451... 
          end
 
          end
 
          else if (detect_r_rdy) begin
 
          else if (detect_r_rdy) begin
 
            state         <=  WRITE;
 
            state         <=  WRITE;
 
            send_sof      <=  1;
 
            send_sof      <=  1;
 
            //bump_buffer[buffer_pos]      <=  rd_dout;
 
            //bump_buffer[buffer_pos]      <=  rd_dout;
 
            write_count   <=  write_count + 1;
 
            write_count   <=  write_count + 13'h1;
 
            //Send First Read
 
            //Send First Read
 
            //read the first packet of data
 
            //read the first packet of data
 
          end
 
          end
 
          else begin
 
          else begin
 
            send_x_rdy      <=  1;
 
            send_x_rdy      <=  1;
Line 466... Line 463... 
        end
 
        end
 
      end
 
      end
 
      WRITE: begin
 
      WRITE: begin
 
        if (!write_ready) begin
 
        if (!write_ready) begin
 
          if (neg_phy_ready && (buffer_pos == 0)) begin
 
          if (neg_phy_ready && (buffer_pos == 0)) begin
 
            buffer_pos        <=  buffer_pos + 1;
 
            buffer_pos        <=  buffer_pos + 4'h1;
 
          end
 
          end
 
 
 
 
 
`ifdef DHOLD_DELAY_EN
 
`ifdef DHOLD_DELAY_EN
 
          if (dhold_delay || !min_holda_timeout) begin
 
          if (dhold_delay || !min_holda_timeout) begin
 
`else
 
`else
Line 489... Line 486... 
            end
 
            end
 
          end
 
          end
 
        end
 
        end
 
 
 
 
 
        else begin
 
        else begin
 
          if (write_count <= data_size + 1) begin
 
          if (write_count <= data_size + 1) begin //is this data_size + 1 for the CRC?
 
            if (buffer_pos > 0) begin
 
            if (buffer_pos > 0) begin
 
              buffer_pos      <=  buffer_pos - 1;
 
              buffer_pos      <=  buffer_pos - 1;
 
              if (buffer_pos == 1) begin
 
              if (buffer_pos == 1) begin
 
                write_count   <=  write_count + 1;
 
                write_count   <=  write_count + 13'h1;
 
              end
 
              end
 
            end
 
            end
 
            else begin
 
            else begin
 
              write_count     <=  write_count + 1;
 
              write_count     <=  write_count + 13'h1;
 
            end
 
            end
 
          end
 
          end
 
          else begin
 
          else begin
 
           send_eof          <=  1;
 
           send_eof          <=  1;
 
           state             <=  WAIT_RESPONSE;
 
           state             <=  WAIT_RESPONSE;
Line 514... Line 511... 
`else
 
`else
 
        if (detect_hold && (buffer_pos == 0)) begin
 
        if (detect_hold && (buffer_pos == 0)) begin
 
`endif
 
`endif
 
          min_holda_count         <=  0;
 
          min_holda_count         <=  0;
 
//XXX: I may need this to capture holds at the end of a trnasfer
 
//XXX: I may need this to capture holds at the end of a trnasfer
 
          buffer_pos              <=  buffer_pos + 1;
 
          buffer_pos              <=  buffer_pos + 4'h1;
 
          send_holda              <=  1;
 
          send_holda              <=  1;
 
        end
 
        end
 
      end
 
      end
 
      WRITE_END: begin
 
      WRITE_END: begin
 
        state             <=  WAIT_RESPONSE;
 
        state             <=  WAIT_RESPONSE;

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