| Line 29... |
Line 29... |
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input rst, //reset
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input rst, //reset
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input clk,
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input clk,
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input platform_ready, //the underlying physical platform is
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input platform_ready, //the underlying physical platform is
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output platform_error,
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output linkup, //link is finished
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output linkup, //link is finished
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output [31:0] tx_dout,
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output [31:0] tx_dout,
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output tx_isk,
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output tx_is_k,
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output tx_comm_reset,
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output tx_comm_reset,
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output tx_comm_wake,
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output tx_comm_wake,
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output tx_elec_idle,
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output tx_elec_idle,
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input tx_oob_complete,
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input [31:0] rx_din,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input [3:0] rx_is_k,
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input rx_elec_idle,
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input rx_elec_idle,
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input rx_byte_is_aligned,
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input rx_byte_is_aligned,
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input comm_init_detect,
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input comm_init_detect,
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input comm_wake_detect,
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input comm_wake_detect,
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output phy_ready,
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output phy_ready,
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input phy_error,
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output [3:0] lax_state
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output [3:0] lax_state
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);
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);
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//Parameters
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//Parameters
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parameter NOT_READY = 4'h0;
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parameter NOT_READY = 4'h0;
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parameter SEND_FIRST_ALIGN = 4'h1;
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parameter SEND_FIRST_ALIGN = 4'h1;
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parameter SEND_SECOND_ALIGN = 4'h2;
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parameter SEND_SECOND_ALIGN = 4'h2;
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parameter READY = 4'h3;
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parameter READY = 4'h3;
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| Line 62... |
Line 64... |
reg [3:0] state;
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reg [3:0] state;
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reg [7:0] align_count;
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reg [7:0] align_count;
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//OOB Control
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//OOB Control
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wire [31:0] oob_tx_dout;
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wire [31:0] oob_tx_dout;
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wire oob_tx_isk;
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wire oob_tx_is_k;
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//Phy Control
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//Phy Control
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wire [31:0] phy_tx_dout;
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wire [31:0] phy_tx_dout;
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wire phy_tx_isk;
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wire phy_tx_is_k;
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wire align_detected;
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//wire align_detected;
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wire oob_platform_error;
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reg phy_platform_error;
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//Submodules
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//Submodules
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oob_controller oob (
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oob_controller oob (
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.rst (rst),
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.rst (rst),
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.clk (clk),
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.clk (clk),
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//OOB controller
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//OOB controller
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.phy_error (phy_error ),
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.platform_ready (platform_ready),
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.platform_ready (platform_ready),
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.platform_error (oob_platform_error ),
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.linkup (linkup),
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.linkup (linkup),
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//Platform Control
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//Platform Control
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.tx_dout (oob_tx_dout),
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.tx_dout (oob_tx_dout),
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.tx_isk (oob_tx_isk),
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.tx_is_k (oob_tx_is_k ),
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.tx_comm_reset (tx_comm_reset),
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.tx_comm_reset (tx_comm_reset),
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.tx_comm_wake (tx_comm_wake),
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.tx_comm_wake (tx_comm_wake),
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.tx_set_elec_idle (tx_elec_idle),
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.tx_set_elec_idle (tx_elec_idle),
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.tx_oob_complete (tx_oob_complete ),
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.rx_din (rx_din),
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.rx_din (rx_din),
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.rx_isk (rx_isk),
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.rx_is_k (rx_is_k ),
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.comm_init_detect (comm_init_detect),
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.comm_init_detect (comm_init_detect),
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.comm_wake_detect (comm_wake_detect),
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.comm_wake_detect (comm_wake_detect),
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.rx_byte_is_aligned (rx_byte_is_aligned),
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.rx_is_elec_idle (rx_elec_idle),
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.rx_is_elec_idle (rx_elec_idle),
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.rx_byte_is_aligned (rx_byte_is_aligned ),
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.lax_state (lax_state)
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.lax_state (lax_state)
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);
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);
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//Asynchronous Logic
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//Asynchronous Logic
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assign tx_dout = !linkup ? oob_tx_dout : phy_tx_dout;
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assign tx_dout = !linkup ? oob_tx_dout : phy_tx_dout;
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assign tx_isk = !linkup ? oob_tx_isk : phy_tx_isk;
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assign tx_is_k = !linkup ? oob_tx_is_k : phy_tx_is_k;
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assign phy_tx_dout = `PRIM_ALIGN;
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assign phy_tx_dout = `PRIM_ALIGN;
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assign phy_tx_isk = 1;
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assign phy_tx_is_k = 1;
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assign align_detected = ((rx_isk > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
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//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
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//assign phy_ready = ((state == READY) && (!align_detected));
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//assign phy_ready = ((state == READY) && (!align_detected));
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assign phy_ready = (state == READY);
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assign phy_ready = (state == READY);
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assign platform_error = oob_platform_error || phy_platform_error;
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//Synchronous Logic
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//Synchronous Logic
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (rst) begin
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if (rst) begin
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state <= NOT_READY;
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state <= NOT_READY;
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align_count <= 0;
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align_count <= 0;
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phy_platform_error<= 0;
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end
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end
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else begin
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else begin
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if (state == READY) begin
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if (state == READY) begin
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align_count <= align_count + 1;
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align_count <= align_count + 8'h01;
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end
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end
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case (state)
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case (state)
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NOT_READY: begin
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NOT_READY: begin
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align_count <= 0;
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align_count <= 0;
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phy_platform_error <= 0;
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if (linkup) begin
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if (linkup) begin
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`ifdef VERBOSE
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`ifdef VERBOSE
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$display ("sata_phy_layer: linkup! send aligns");
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$display ("sata_phy_layer: linkup! send aligns");
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`endif
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`endif
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state <= SEND_FIRST_ALIGN;
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state <= SEND_FIRST_ALIGN;
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| Line 141... |
Line 147... |
READY: begin
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READY: begin
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if (align_count == 255) begin
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if (align_count == 255) begin
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state <= SEND_FIRST_ALIGN;
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state <= SEND_FIRST_ALIGN;
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`ifdef VERBOSE
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`ifdef VERBOSE
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$display ("sata_phy_layer: linkup! send alignment dwords");
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$display ("sata_phy_layer: linkup! send alignment dwords");
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`else
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$display ("sata_phy_layer: .");
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`endif
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`endif
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//Send an align primitive
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end
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if (phy_error) begin
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phy_platform_error <= 1;
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end
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end
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end
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end
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default: begin
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default: begin
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end
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end
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endcase
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endcase
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