| Line 31... |
Line 31... |
input data_in_clk_valid,
|
input data_in_clk_valid,
|
input data_out_clk,
|
input data_out_clk,
|
input data_out_clk_valid,
|
input data_out_clk_valid,
|
|
|
input platform_ready, //the underlying physical platform is
|
input platform_ready, //the underlying physical platform is
|
output wire linkup, //link is finished
|
output platform_error, //Underlying platform errored out, the
|
output sata_ready,
|
//clock is misaligned, stack should
|
output sata_init,
|
//probably be reset
|
|
output linkup, //link is finished
|
|
|
input send_sync_escape,
|
input send_sync_escape,
|
input [15:0] user_features,
|
input [15:0] user_features,
|
|
|
//User Interface
|
//User Interface
|
output busy,
|
output sata_ready,
|
output error,
|
output sata_busy,
|
|
|
|
output hard_drive_error,
|
|
|
input write_data_en,
|
// input write_data_stb,
|
input single_rdwr,
|
// input read_data_stb,
|
input read_data_en,
|
|
|
|
input send_user_command_stb,
|
input execute_command_stb,
|
input soft_reset_en,
|
input command_layer_reset,
|
input [7:0] command,
|
input [7:0] hard_drive_command,
|
output pio_data_ready,
|
output pio_data_ready,
|
|
|
input [15:0] sector_count,
|
input [15:0] sector_count,
|
input [47:0] sector_address,
|
input [47:0] sector_address,
|
|
|
| Line 61... |
Line 62... |
output dma_activate_stb,
|
output dma_activate_stb,
|
output d2h_reg_stb,
|
output d2h_reg_stb,
|
output pio_setup_stb,
|
output pio_setup_stb,
|
output d2h_data_stb,
|
output d2h_data_stb,
|
output dma_setup_stb,
|
output dma_setup_stb,
|
output wire set_device_bits_stb,
|
output set_device_bits_stb,
|
|
|
output dbg_send_command_stb,
|
|
output dbg_send_control_stb,
|
|
output dbg_send_data_stb,
|
|
|
|
|
output [7:0] d2h_fis,
|
output d2h_interrupt,
|
output d2h_interrupt,
|
output d2h_notification,
|
output d2h_notification,
|
output [3:0] d2h_port_mult,
|
output [3:0] d2h_port_mult,
|
output [7:0] d2h_device,
|
output [7:0] d2h_device,
|
output [47:0] d2h_lba,
|
output [47:0] d2h_lba,
|
| Line 81... |
Line 79... |
input [31:0] user_din,
|
input [31:0] user_din,
|
input user_din_stb,
|
input user_din_stb,
|
output [1:0] user_din_ready,
|
output [1:0] user_din_ready,
|
input [1:0] user_din_activate,
|
input [1:0] user_din_activate,
|
output [23:0] user_din_size,
|
output [23:0] user_din_size,
|
|
output user_din_empty,
|
|
|
output [31:0] user_dout,
|
output [31:0] user_dout,
|
output user_dout_ready,
|
output user_dout_ready,
|
input user_dout_activate,
|
input user_dout_activate,
|
input user_dout_stb,
|
input user_dout_stb,
|
| Line 96... |
Line 95... |
output phy_ready,
|
output phy_ready,
|
|
|
//Buffer
|
//Buffer
|
//Platform Interface
|
//Platform Interface
|
output [31:0] tx_dout,
|
output [31:0] tx_dout,
|
output tx_isk,
|
output tx_is_k, //Connect All 4 'tx_is_k'to this signal
|
output tx_comm_reset,
|
output tx_comm_reset,
|
output tx_comm_wake,
|
output tx_comm_wake,
|
output tx_elec_idle,
|
output tx_elec_idle,
|
|
|
input [31:0] rx_din,
|
input [31:0] rx_din,
|
input [3:0] rx_isk,
|
input [3:0] rx_is_k,
|
input rx_elec_idle,
|
input rx_elec_idle,
|
|
input rx_byte_is_aligned,
|
input comm_init_detect,
|
input comm_init_detect,
|
input comm_wake_detect,
|
input comm_wake_detect,
|
input rx_byte_is_aligned,
|
input tx_oob_complete,
|
|
input phy_error,
|
|
|
//Debug
|
|
output dbg_remote_abort,
|
|
output dbg_xmit_error,
|
|
output dbg_read_crc_error,
|
|
|
|
//PIO
|
|
output dbg_pio_response,
|
|
output dbg_pio_direction,
|
|
output [15:0] dbg_pio_transfer_count,
|
|
output [7:0] dbg_pio_e_status,
|
|
|
|
//Host dbg_ to Device Regster Values
|
|
output [7:0] dbg_h2d_command,
|
|
output [15:0] dbg_h2d_features,
|
|
output [7:0] dbg_h2d_control,
|
|
output [3:0] dbg_h2d_port_mult,
|
|
output [7:0] dbg_h2d_device,
|
|
output [47:0] dbg_h2d_lba,
|
|
output [15:0] dbg_h2d_sector_count,
|
|
|
|
//DMA Specific Control
|
//DMA Specific Control
|
|
|
//Data Control
|
//Data Control
|
output dbg_cl_if_ready,
|
|
output dbg_cl_if_activate,
|
|
output [23:0] dbg_cl_if_size,
|
|
output dbg_cl_if_strobe,
|
|
output [31:0] dbg_cl_if_data,
|
|
|
|
output [1:0] dbg_cl_of_ready,
|
|
output [1:0] dbg_cl_of_activate,
|
|
output dbg_cl_of_strobe,
|
|
output [31:0] dbg_cl_of_data,
|
|
output [23:0] dbg_cl_of_size,
|
|
|
|
output [3:0] dbg_cc_lax_state,
|
output [3:0] dbg_cc_lax_state,
|
output [3:0] dbg_cr_lax_state,
|
|
output [3:0] dbg_cw_lax_state,
|
output [3:0] dbg_cw_lax_state,
|
|
|
output [3:0] dbg_t_lax_state,
|
output [3:0] dbg_t_lax_state,
|
|
|
output [3:0] dbg_li_lax_state,
|
output [3:0] dbg_li_lax_state,
|
| Line 161... |
Line 128... |
input prim_scrambler_en,
|
input prim_scrambler_en,
|
input data_scrambler_en,
|
input data_scrambler_en,
|
|
|
output dbg_ll_write_ready,
|
output dbg_ll_write_ready,
|
output dbg_ll_paw,
|
output dbg_ll_paw,
|
output dbg_ll_write_start,
|
|
output dbg_ll_write_strobe,
|
output dbg_ll_write_strobe,
|
output dbg_ll_write_finished,
|
|
output [31:0] dbg_ll_write_data,
|
|
output [31:0] dbg_ll_write_size,
|
|
output dbg_ll_write_hold,
|
|
output dbg_ll_write_abort,
|
|
|
|
output dbg_ll_read_start,
|
|
output dbg_ll_read_strobe,
|
|
output [31:0] dbg_ll_read_data,
|
|
output dbg_ll_read_ready,
|
|
output dbg_ll_read_finished,
|
|
output dbg_ll_remote_abort,
|
|
output dbg_ll_xmit_error,
|
|
|
|
output dbg_ll_send_crc,
|
output dbg_ll_send_crc,
|
|
|
//Phy Layer
|
//Phy Layer
|
output [3:0] lax_state,
|
output [3:0] oob_state,
|
|
|
//Primative Detection
|
//Primative Detection
|
output dbg_detect_sync,
|
output dbg_detect_sync,
|
output dbg_detect_r_rdy,
|
output dbg_detect_r_rdy,
|
output dbg_detect_r_ip,
|
output dbg_detect_r_ip,
|
| Line 235... |
Line 187... |
wire ll_sync_escape;
|
wire ll_sync_escape;
|
wire ll_write_start;
|
wire ll_write_start;
|
wire ll_write_strobe;
|
wire ll_write_strobe;
|
wire ll_write_finished;
|
wire ll_write_finished;
|
wire [31:0] ll_write_data;
|
wire [31:0] ll_write_data;
|
wire [31:0] ll_write_size;
|
wire [23:0] ll_write_size;
|
wire ll_write_hold;
|
wire ll_write_hold;
|
wire ll_write_abort;
|
wire ll_write_abort;
|
|
|
|
|
wire ll_read_ready;
|
wire ll_read_ready;
|
| Line 250... |
Line 202... |
wire ll_read_crc_ok;
|
wire ll_read_crc_ok;
|
wire ll_remote_abort;
|
wire ll_remote_abort;
|
wire ll_xmit_error;
|
wire ll_xmit_error;
|
|
|
wire [31:0] ll_tx_dout;
|
wire [31:0] ll_tx_dout;
|
wire ll_tx_isk;
|
wire ll_tx_is_k;
|
|
|
//Phy Layer
|
//Phy Layer
|
wire [31:0] phy_tx_dout;
|
wire [31:0] phy_tx_dout;
|
wire phy_tx_isk;
|
wire phy_tx_is_k;
|
|
|
//User Interface state machine
|
//User Interface state machine
|
|
|
//Transport Layer
|
//Transport Layer
|
wire sync_escape;
|
wire sync_escape;
|
| Line 269... |
Line 221... |
wire [3:0] h2d_port_mult;
|
wire [3:0] h2d_port_mult;
|
wire [7:0] h2d_device;
|
wire [7:0] h2d_device;
|
wire [47:0] h2d_lba;
|
wire [47:0] h2d_lba;
|
wire [15:0] h2d_sector_count;
|
wire [15:0] h2d_sector_count;
|
|
|
|
|
wire remote_abort;
|
wire remote_abort;
|
wire xmit_error;
|
wire xmit_error;
|
wire read_crc_error;
|
wire read_crc_error;
|
|
|
//PIO
|
//PIO
|
| Line 293... |
Line 244... |
wire [1:0] cl_of_activate;
|
wire [1:0] cl_of_activate;
|
wire cl_of_strobe;
|
wire cl_of_strobe;
|
wire [31:0] cl_of_data;
|
wire [31:0] cl_of_data;
|
wire [23:0] cl_of_size;
|
wire [23:0] cl_of_size;
|
|
|
|
|
//Link Layer Interface
|
//Link Layer Interface
|
wire t_sync_escape;
|
wire t_sync_escape;
|
wire t_write_start;
|
wire t_write_start;
|
wire t_write_strobe;
|
wire t_write_strobe;
|
wire t_write_finished;
|
wire t_write_finished;
|
wire [31:0] t_write_data;
|
wire [31:0] t_write_data;
|
wire [31:0] t_write_size;
|
wire [23:0] t_write_size;
|
wire t_write_hold;
|
wire t_write_hold;
|
wire t_write_abort;
|
wire t_write_abort;
|
wire t_xmit_error;
|
wire t_xmit_error;
|
|
|
wire t_read_start;
|
wire t_read_start;
|
| Line 312... |
Line 262... |
wire [31:0] t_read_data;
|
wire [31:0] t_read_data;
|
wire t_read_strobe;
|
wire t_read_strobe;
|
wire t_read_finished;
|
wire t_read_finished;
|
wire t_read_crc_ok;
|
wire t_read_crc_ok;
|
wire t_remote_abort;
|
wire t_remote_abort;
|
|
|
//Comand Layer registers
|
//Comand Layer registers
|
|
|
//Submodules
|
//Submodules
|
sata_command_layer scl (
|
sata_command_layer scl (
|
.rst (rst ),
|
.rst (rst ),
|
| Line 326... |
Line 275... |
.data_in_clk_valid (data_in_clk_valid ),
|
.data_in_clk_valid (data_in_clk_valid ),
|
.data_out_clk (data_out_clk ),
|
.data_out_clk (data_out_clk ),
|
.data_out_clk_valid (data_out_clk_valid ),
|
.data_out_clk_valid (data_out_clk_valid ),
|
|
|
//Application Interface
|
//Application Interface
|
.sata_init (sata_init ),
|
|
.command_layer_ready (sata_ready ),
|
.command_layer_ready (sata_ready ),
|
.busy (busy ),
|
.sata_busy (sata_busy ),
|
.dev_error (error ),
|
.hard_drive_error (hard_drive_error ),
|
.send_sync_escape (send_sync_escape ),
|
.send_sync_escape (send_sync_escape ),
|
.user_features (user_features ),
|
.user_features (user_features ),
|
|
|
.write_data_en (write_data_en ),
|
// .write_data_stb (write_data_stb ),
|
.single_rdwr (single_rdwr ),
|
// .read_data_stb (read_data_stb ),
|
.read_data_en (read_data_en ),
|
.execute_command_stb (execute_command_stb ),
|
|
|
.send_user_command_stb(send_user_command_stb ),
|
.command_layer_reset (command_layer_reset ),
|
.soft_reset_en (soft_reset_en ),
|
.hard_drive_command (hard_drive_command ),
|
.command (command ),
|
|
.pio_data_ready (pio_data_ready ),
|
.pio_data_ready (pio_data_ready ),
|
|
|
.sector_count (sector_count ),
|
.sector_count (sector_count ),
|
.sector_address (sector_address ),
|
.sector_address (sector_address ),
|
|
|
.user_din (user_din ),
|
.user_din (user_din ),
|
.user_din_stb (user_din_stb ),
|
.user_din_stb (user_din_stb ),
|
.user_din_ready (user_din_ready ),
|
.user_din_ready (user_din_ready ),
|
.user_din_activate (user_din_activate ),
|
.user_din_activate (user_din_activate ),
|
.user_din_size (user_din_size ),
|
.user_din_size (user_din_size ),
|
|
.user_din_empty (user_din_empty ),
|
|
|
.user_dout (user_dout ),
|
.user_dout (user_dout ),
|
.user_dout_ready (user_dout_ready ),
|
.user_dout_ready (user_dout_ready ),
|
.user_dout_activate (user_dout_activate ),
|
.user_dout_activate (user_dout_activate ),
|
.user_dout_stb (user_dout_stb ),
|
.user_dout_stb (user_dout_stb ),
|
| Line 416... |
Line 364... |
.t_of_ready (of_ready ),
|
.t_of_ready (of_ready ),
|
.t_of_activate (of_activate ),
|
.t_of_activate (of_activate ),
|
.t_of_size (of_size ),
|
.t_of_size (of_size ),
|
|
|
.cl_c_state (dbg_cc_lax_state ),
|
.cl_c_state (dbg_cc_lax_state ),
|
.cl_r_state (dbg_cr_lax_state ),
|
|
.cl_w_state (dbg_cw_lax_state )
|
.cl_w_state (dbg_cw_lax_state )
|
|
|
|
|
|
|
);
|
);
|
|
|
|
|
|
|
//Transport Layer
|
//Transport Layer
|
sata_transport_layer stl (
|
sata_transport_layer stl (
|
.rst (rst | !linkup ),
|
.rst (rst | !linkup ),
|
.clk (clk ),
|
.clk (clk ),
|
.phy_ready (phy_ready ),
|
.phy_ready (phy_ready ),
|
| Line 466... |
Line 409... |
.h2d_device (h2d_device ),
|
.h2d_device (h2d_device ),
|
.h2d_lba (h2d_lba ),
|
.h2d_lba (h2d_lba ),
|
.h2d_sector_count (h2d_sector_count ),
|
.h2d_sector_count (h2d_sector_count ),
|
|
|
//Device to Host Register Values
|
//Device to Host Register Values
|
|
.d2h_fis (d2h_fis ),
|
.d2h_interrupt (d2h_interrupt ),
|
.d2h_interrupt (d2h_interrupt ),
|
.d2h_notification (d2h_notification ),
|
.d2h_notification (d2h_notification ),
|
.d2h_port_mult (d2h_port_mult ),
|
.d2h_port_mult (d2h_port_mult ),
|
.d2h_device (d2h_device ),
|
.d2h_device (d2h_device ),
|
.d2h_lba (d2h_lba ),
|
.d2h_lba (d2h_lba ),
|
| Line 550... |
Line 494... |
|
|
//Phy Layer
|
//Phy Layer
|
.phy_ready (phy_ready ),
|
.phy_ready (phy_ready ),
|
.platform_ready (platform_ready ),
|
.platform_ready (platform_ready ),
|
.tx_dout (ll_tx_dout ),
|
.tx_dout (ll_tx_dout ),
|
.tx_isk (ll_tx_isk ),
|
.tx_is_k (ll_tx_is_k ),
|
|
|
.rx_din (rx_din ),
|
.rx_din (rx_din ),
|
.rx_isk (rx_isk ),
|
.rx_is_k (rx_is_k ),
|
.is_device (1'b0 ),
|
.is_device (1'b0 ),
|
|
|
//Primative Detection
|
//Primative Detection
|
.detect_sync (dbg_detect_sync ),
|
.detect_sync (dbg_detect_sync ),
|
.detect_r_rdy (dbg_detect_r_rdy ),
|
.detect_r_rdy (dbg_detect_r_rdy ),
|
| Line 601... |
Line 545... |
.rst (rst ),
|
.rst (rst ),
|
.clk (clk ),
|
.clk (clk ),
|
|
|
//Control/Status
|
//Control/Status
|
.platform_ready (platform_ready ),
|
.platform_ready (platform_ready ),
|
|
.platform_error (platform_error ),
|
.linkup (linkup ),
|
.linkup (linkup ),
|
|
|
//Platform Interface
|
//Platform Interface
|
.tx_dout (phy_tx_dout ),
|
.tx_dout (phy_tx_dout ),
|
.tx_isk (phy_tx_isk ),
|
.tx_is_k (phy_tx_is_k ),
|
.tx_comm_reset (tx_comm_reset ),
|
.tx_comm_reset (tx_comm_reset ),
|
.tx_comm_wake (tx_comm_wake ),
|
.tx_comm_wake (tx_comm_wake ),
|
.tx_elec_idle (tx_elec_idle ),
|
.tx_elec_idle (tx_elec_idle ),
|
|
.tx_oob_complete (tx_oob_complete ),
|
|
|
.rx_din (rx_din ),
|
.rx_din (rx_din ),
|
.rx_isk (rx_isk ),
|
.rx_is_k (rx_is_k ),
|
.comm_init_detect (comm_init_detect ),
|
.comm_init_detect (comm_init_detect ),
|
.comm_wake_detect (comm_wake_detect ),
|
.comm_wake_detect (comm_wake_detect ),
|
.rx_elec_idle (rx_elec_idle ),
|
.rx_elec_idle (rx_elec_idle ),
|
.rx_byte_is_aligned (rx_byte_is_aligned ),
|
.rx_byte_is_aligned (rx_byte_is_aligned ),
|
|
.phy_error (phy_error ),
|
|
|
.lax_state (lax_state ),
|
.lax_state (oob_state ),
|
.phy_ready (phy_ready )
|
.phy_ready (phy_ready )
|
);
|
);
|
|
|
|
|
|
|
//Asynchronous Logic
|
//Asynchronous Logic
|
|
|
//control of data to the platform controller
|
//control of data to the platform controller
|
|
//In order to send align primitives the phy must sometimes take over the bus
|
assign tx_dout = (phy_ready) ? ll_tx_dout : phy_tx_dout;
|
assign tx_dout = (phy_ready) ? ll_tx_dout : phy_tx_dout;
|
assign tx_isk = (phy_ready) ? ll_tx_isk : phy_tx_isk;
|
assign tx_is_k = (phy_ready) ? ll_tx_is_k : phy_tx_is_k;
|
|
|
//no activity on the stack
|
//no activity on the stack
|
|
|
//Debug
|
//Debug
|
assign ll_write_start = t_write_start;
|
assign ll_write_start = t_write_start;
|
assign dbg_ll_write_start = t_write_start;
|
|
assign ll_write_data = t_write_data;
|
assign ll_write_data = t_write_data;
|
assign dbg_ll_write_data = t_write_data;
|
|
assign ll_write_hold = t_write_hold;
|
assign ll_write_hold = t_write_hold;
|
assign dbg_ll_write_hold = t_write_hold;
|
|
assign ll_write_size = t_write_size;
|
assign ll_write_size = t_write_size;
|
assign dbg_ll_write_size = t_write_size;
|
|
assign ll_write_abort = t_write_abort;
|
assign ll_write_abort = t_write_abort;
|
assign dbg_ll_write_abort = t_write_abort;
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assign ll_read_ready = t_read_ready;
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assign ll_read_ready = t_read_ready;
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assign dbg_ll_read_ready = t_read_ready;
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assign ll_sync_escape = t_sync_escape;
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assign ll_sync_escape = t_sync_escape;
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assign dbg_ll_write_strobe = ll_write_strobe;
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assign t_write_strobe = ll_write_strobe;
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assign t_write_strobe = ll_write_strobe;
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assign dbg_ll_write_finished = ll_write_finished;
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assign t_write_finished = ll_write_finished;
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assign t_write_finished = ll_write_finished;
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assign dbg_ll_read_strobe = ll_read_strobe;
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assign dbg_ll_read_start = ll_read_start;
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assign dbg_ll_read_finished = ll_read_finished;
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assign dbg_ll_read_data = ll_read_data;
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assign dbg_ll_remote_abort = ll_remote_abort;
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assign dbg_ll_xmit_error = ll_xmit_error;
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assign t_read_strobe = ll_read_strobe;
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assign t_read_strobe = ll_read_strobe;
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assign t_read_start = ll_read_start;
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assign t_read_start = ll_read_start;
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assign t_read_finished = ll_read_finished;
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assign t_read_finished = ll_read_finished;
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assign t_read_data = ll_read_data;
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assign t_read_data = ll_read_data;
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assign t_remote_abort = ll_remote_abort;
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assign t_remote_abort = ll_remote_abort;
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assign t_xmit_error = ll_xmit_error;
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assign t_xmit_error = ll_xmit_error;
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assign t_read_crc_ok = ll_read_crc_ok;
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assign t_read_crc_ok = ll_read_crc_ok;
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assign dbg_send_command_stb = send_command_stb;
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assign dbg_send_control_stb = send_control_stb;
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assign dbg_send_data_stb = send_data_stb;
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assign dbg_remote_abort = remote_abort;
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assign dbg_xmit_error = xmit_error;
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assign dbg_read_crc_error = read_crc_error;
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assign dbg_h2d_command = h2d_command;
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assign dbg_h2d_features = h2d_features;
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assign dbg_h2d_control = h2d_control;
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assign dbg_h2d_port_mult = h2d_port_mult;
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assign dbg_h2d_device = h2d_device;
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assign dbg_h2d_sector_count = h2d_sector_count;
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assign cl_if_ready = if_ready;
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assign cl_if_ready = if_ready;
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assign dbg_cl_if_activate = cl_if_activate;
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assign if_activate = cl_if_activate;
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assign if_activate = cl_if_activate;
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assign dbg_cl_if_size = if_size;
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assign cl_if_size = if_size;
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assign cl_if_size = if_size;
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assign dbg_cl_if_strobe = cl_if_strobe;
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assign if_strobe = cl_if_strobe;
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assign if_strobe = cl_if_strobe;
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assign dbg_cl_if_data = if_data;
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assign cl_if_data = if_data;
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assign cl_if_data = if_data;
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assign cl_of_ready = of_ready;
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assign cl_of_ready = of_ready;
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assign dbg_cl_of_ready = of_ready;
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assign of_activate = cl_of_activate;
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assign of_activate = cl_of_activate;
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assign dbg_cl_of_activate = cl_of_activate;
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assign of_strobe = cl_of_strobe;
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assign of_strobe = cl_of_strobe;
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assign dbg_cl_of_strobe = cl_of_strobe;
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assign of_data = cl_of_data;
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assign of_data = cl_of_data;
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assign dbg_cl_of_data = cl_of_data;
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assign cl_of_size = of_size;
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assign cl_of_size = of_size;
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assign dbg_cl_of_size = of_size;
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//Synchronous Logic
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//Synchronous Logic
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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