| Line 9... |
Line 9... |
input rst, //reset
|
input rst, //reset
|
input clk,
|
input clk,
|
|
|
output linkup, //link is finished
|
output linkup, //link is finished
|
output sata_ready,
|
output sata_ready,
|
output busy,
|
output sata_busy,
|
|
|
input write_data_en,
|
//input write_data_stb,
|
input read_data_en,
|
//input read_data_stb,
|
|
input [7:0] hard_drive_command,
|
|
input execute_command_stb,
|
|
|
input soft_reset_en,
|
input command_layer_reset,
|
input [15:0] sector_count,
|
input [15:0] sector_count,
|
input [47:0] sector_address,
|
input [47:0] sector_address,
|
|
|
output d2h_interrupt,
|
output d2h_interrupt,
|
output d2h_notification,
|
output d2h_notification,
|
| Line 59... |
Line 61... |
input single_rdwr
|
input single_rdwr
|
);
|
);
|
reg [31:0] test_id = 0;
|
reg [31:0] test_id = 0;
|
|
|
wire [31:0] tx_dout;
|
wire [31:0] tx_dout;
|
wire tx_isk;
|
wire tx_is_k;
|
wire tx_comm_reset;
|
wire tx_comm_reset;
|
wire tx_comm_wake;
|
wire tx_comm_wake;
|
wire tx_elec_idle;
|
wire tx_elec_idle;
|
|
|
wire [31:0] rx_din;
|
wire [31:0] rx_din;
|
wire [3:0] rx_isk;
|
wire [3:0] rx_is_k;
|
wire rx_elec_idle;
|
wire rx_elec_idle;
|
wire comm_init_detect;
|
wire comm_init_detect;
|
wire comm_wake_detect;
|
wire comm_wake_detect;
|
|
|
wire rx_byte_is_aligned;
|
|
|
|
reg r_rst;
|
reg r_rst;
|
reg r_write_data_en;
|
reg r_write_data_stb;
|
reg r_read_data_en;
|
reg r_read_data_stb;
|
reg r_soft_reset_en;
|
reg r_command_layer_reset;
|
reg [15:0] r_sector_count;
|
reg [15:0] r_sector_count;
|
reg [47:0] r_sector_address;
|
reg [47:0] r_sector_address;
|
reg r_prim_scrambler_en;
|
reg r_prim_scrambler_en;
|
reg r_data_scrambler_en;
|
reg r_data_scrambler_en;
|
reg r_platform_ready;
|
reg r_platform_ready;
|
reg r_dout_count;
|
reg r_dout_count;
|
reg r_hold;
|
reg r_hold;
|
reg r_single_rdwr;
|
|
|
|
reg r_u2h_write_enable;
|
reg r_u2h_write_enable;
|
reg [23:0] r_u2h_write_count;
|
reg [23:0] r_u2h_write_count;
|
reg r_h2u_read_enable;
|
reg r_h2u_read_enable;
|
|
|
|
reg [7:0] r_hard_drive_command;
|
|
reg r_execute_command_stb;
|
|
|
wire hd_read_from_host;
|
wire hd_read_from_host;
|
wire [31:0] hd_data_from_host;
|
wire [31:0] hd_data_from_host;
|
|
|
|
|
wire hd_write_to_host;
|
wire hd_write_to_host;
|
| Line 109... |
Line 111... |
wire user_din_stb;
|
wire user_din_stb;
|
wire [1:0] user_din_ready;
|
wire [1:0] user_din_ready;
|
wire [1:0] user_din_activate;
|
wire [1:0] user_din_activate;
|
wire [23:0] user_din_size;
|
wire [23:0] user_din_size;
|
|
|
|
wire dma_activate_stb;
|
|
wire d2h_reg_stb;
|
|
wire pio_setup_stb;
|
|
wire d2h_data_stb;
|
|
wire dma_setup_stb;
|
|
wire set_device_bits_stb;
|
|
wire [7:0] d2h_fis;
|
|
wire i_rx_byte_is_aligned;
|
|
|
|
|
|
|
|
|
|
|
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
|
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
|
always @ (*) r_rst = rst;
|
always @ (*) r_rst = rst;
|
always @ (*) r_write_data_en = write_data_en;
|
//always @ (*) r_write_data_stb = write_data_stb;
|
always @ (*) r_read_data_en = read_data_en;
|
//always @ (*) r_read_data_stb = read_data_stb;
|
always @ (*) r_soft_reset_en = soft_reset_en;
|
always @ (*) r_command_layer_reset= command_layer_reset;
|
always @ (*) r_sector_count = sector_count;
|
always @ (*) r_sector_count = sector_count;
|
always @ (*) r_sector_address = sector_address;
|
always @ (*) r_sector_address = sector_address;
|
always @ (*) r_prim_scrambler_en = prim_scrambler_en;
|
always @ (*) r_prim_scrambler_en = prim_scrambler_en;
|
always @ (*) r_data_scrambler_en = data_scrambler_en;
|
always @ (*) r_data_scrambler_en = data_scrambler_en;
|
always @ (*) r_platform_ready = platform_ready;
|
always @ (*) r_platform_ready = platform_ready;
|
always @ (*) r_hold = hold;
|
always @ (*) r_hold = hold;
|
always @ (*) r_single_rdwr = single_rdwr;
|
|
|
|
always @ (*) r_u2h_write_enable = u2h_write_enable;
|
always @ (*) r_u2h_write_enable = u2h_write_enable;
|
always @ (*) r_u2h_write_count = u2h_write_count;
|
always @ (*) r_u2h_write_count = u2h_write_count;
|
|
|
always @ (*) r_h2u_read_enable = h2u_read_enable;
|
always @ (*) r_h2u_read_enable = h2u_read_enable;
|
|
|
|
always @ (*) r_hard_drive_command = hard_drive_command;
|
|
always @ (*) r_execute_command_stb= execute_command_stb;
|
|
|
//Submodules
|
//Submodules
|
|
|
//User Generated Test Data
|
//User Generated Test Data
|
test_in user_2_hd_generator(
|
test_in user_2_hd_generator(
|
.clk (clk ),
|
.clk (clk ),
|
| Line 185... |
Line 202... |
);
|
);
|
|
|
sata_stack ss (
|
sata_stack ss (
|
.rst (r_rst ), //reset
|
.rst (r_rst ), //reset
|
.clk (clk ), //clock used to run the stack
|
.clk (clk ), //clock used to run the stack
|
.data_in_clk (clk ),
|
.command_layer_reset (r_command_layer_reset),
|
.data_in_clk_valid (1'b1 ),
|
|
.data_out_clk (clk ),
|
|
.data_out_clk_valid (1'b1 ),
|
|
|
|
.platform_ready (platform_ready ), //the underlying physical platform is
|
.platform_ready (platform_ready ), //the underlying physical platform is
|
|
.platform_error ( ),
|
.linkup (linkup ), //link is finished
|
.linkup (linkup ), //link is finished
|
|
|
.sata_ready (sata_ready ),
|
.sata_ready (sata_ready ),
|
|
.sata_busy (sata_busy ),
|
|
|
.busy (busy ),
|
.send_sync_escape (1'b0 ),
|
|
.hard_drive_error ( ),
|
|
|
.write_data_en (r_write_data_en ),
|
.pio_data_ready ( ),
|
.single_rdwr (r_single_rdwr ),
|
|
.read_data_en (r_read_data_en ),
|
|
|
|
.send_user_command_stb (1'b0 ),
|
|
.soft_reset_en (r_soft_reset_en ),
|
|
.command (1'b0 ),
|
|
|
|
|
//Host to Device Control
|
|
// .write_data_stb (r_write_data_stb ),
|
|
// .read_data_stb (r_read_data_stb ),
|
|
.hard_drive_command (r_hard_drive_command ),
|
|
.execute_command_stb (r_execute_command_stb),
|
|
.user_features (16'h0000 ),
|
.sector_count (r_sector_count ),
|
.sector_count (r_sector_count ),
|
.sector_address (r_sector_address ),
|
.sector_address (r_sector_address ),
|
|
|
|
.dma_activate_stb (dma_activate_stb ),
|
|
.d2h_reg_stb (d2h_reg_stb ),
|
|
.pio_setup_stb (pio_setup_stb ),
|
|
.d2h_data_stb (d2h_data_stb ),
|
|
.dma_setup_stb (dma_setup_stb ),
|
|
.set_device_bits_stb (set_device_bits_stb ),
|
|
|
|
.d2h_fis (d2h_fis ),
|
.d2h_interrupt (d2h_interrupt ),
|
.d2h_interrupt (d2h_interrupt ),
|
.d2h_notification (d2h_notification ),
|
.d2h_notification (d2h_notification ),
|
.d2h_port_mult (d2h_port_mult ),
|
.d2h_port_mult (d2h_port_mult ),
|
.d2h_device (d2h_device ),
|
.d2h_device (d2h_device ),
|
.d2h_lba (d2h_lba ),
|
.d2h_lba (d2h_lba ),
|
.d2h_sector_count (d2h_sector_count ),
|
.d2h_sector_count (d2h_sector_count ),
|
.d2h_status (d2h_status ),
|
.d2h_status (d2h_status ),
|
.d2h_error (d2h_error ),
|
.d2h_error (d2h_error ),
|
|
|
|
//Data from host to the hard drive path
|
|
.data_in_clk (clk ),
|
|
.data_in_clk_valid (1'b1 ),
|
.user_din (user_din ), //User Data Here
|
.user_din (user_din ), //User Data Here
|
.user_din_stb (user_din_stb ), //Strobe Each Data word in here
|
.user_din_stb (user_din_stb ), //Strobe Each Data word in here
|
.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
|
.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
|
.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
|
.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
|
.user_din_size (user_din_size ), //Find the size of the data to write to the device
|
.user_din_size (user_din_size ), //Find the size of the data to write to the device
|
|
|
|
//Data from hard drive to host path
|
|
.data_out_clk (clk ),
|
|
.data_out_clk_valid (1'b1 ),
|
.user_dout (user_dout ),
|
.user_dout (user_dout ),
|
.user_dout_ready (user_dout_ready ),
|
.user_dout_ready (user_dout_ready ),
|
.user_dout_activate (user_dout_activate ),
|
.user_dout_activate (user_dout_activate ),
|
.user_dout_stb (user_dout_stb ),
|
.user_dout_stb (user_dout_stb ),
|
.user_dout_size (user_dout_size ),
|
.user_dout_size (user_dout_size ),
|
|
|
.transport_layer_ready (transport_layer_ready),
|
.transport_layer_ready (transport_layer_ready),
|
.link_layer_ready (link_layer_ready ),
|
.link_layer_ready (link_layer_ready ),
|
.phy_ready (phy_ready ),
|
.phy_ready (phy_ready ),
|
|
.phy_error (1'b0 ),
|
|
|
.tx_dout (tx_dout ),
|
.tx_dout (tx_dout ),
|
.tx_isk (tx_isk ),
|
.tx_is_k (tx_is_k ),
|
.tx_comm_reset (tx_comm_reset ),
|
.tx_comm_reset (tx_comm_reset ),
|
.tx_comm_wake (tx_comm_wake ),
|
.tx_comm_wake (tx_comm_wake ),
|
.tx_elec_idle (tx_elec_idle ),
|
.tx_elec_idle (tx_elec_idle ),
|
|
.tx_oob_complete (1'b1 ),
|
|
|
.rx_din (rx_din ),
|
.rx_din (rx_din ),
|
.rx_isk (rx_isk ),
|
.rx_is_k (rx_is_k ),
|
.rx_elec_idle (rx_elec_idle ),
|
.rx_elec_idle (rx_elec_idle ),
|
|
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
|
.comm_init_detect (comm_init_detect ),
|
.comm_init_detect (comm_init_detect ),
|
.comm_wake_detect (comm_wake_detect ),
|
.comm_wake_detect (comm_wake_detect ),
|
.rx_byte_is_aligned (rx_byte_is_aligned ),
|
|
|
|
|
|
.prim_scrambler_en (r_prim_scrambler_en ),
|
//.prim_scrambler_en (r_prim_scrambler_en ),
|
.data_scrambler_en (r_data_scrambler_en )
|
.prim_scrambler_en (1'b1 ),
|
|
//.data_scrambler_en (r_data_scrambler_en )
|
|
.data_scrambler_en (1'b1 )
|
);
|
);
|
|
|
faux_sata_hd fshd (
|
faux_sata_hd fshd (
|
.rst (r_rst ),
|
.rst (r_rst ),
|
.clk (clk ),
|
.clk (clk ),
|
.tx_dout (rx_din ),
|
.tx_dout (rx_din ),
|
.tx_isk (rx_isk ),
|
.tx_is_k (rx_is_k ),
|
|
|
.rx_din (tx_dout ),
|
.rx_din (tx_dout ),
|
.rx_isk ({3'b000, tx_isk} ),
|
.rx_is_k ({3'b000, tx_is_k} ),
|
.rx_is_elec_idle (tx_elec_idle ),
|
.rx_is_elec_idle (tx_elec_idle ),
|
.rx_byte_is_aligned (rx_byte_is_aligned ),
|
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
|
|
|
.comm_reset_detect (tx_comm_reset ),
|
.comm_reset_detect (tx_comm_reset ),
|
.comm_wake_detect (tx_comm_wake ),
|
.comm_wake_detect (tx_comm_wake ),
|
|
|
.tx_comm_reset (comm_init_detect ),
|
.tx_comm_reset (comm_init_detect ),
|
| Line 271... |
Line 307... |
|
|
.hd_ready (hd_ready ),
|
.hd_ready (hd_ready ),
|
// .phy_ready (phy_ready ),
|
// .phy_ready (phy_ready ),
|
|
|
|
|
.dbg_data_scrambler_en (r_data_scrambler_en ),
|
//.dbg_data_scrambler_en (r_data_scrambler_en ),
|
|
.dbg_data_scrambler_en (1'b1 ),
|
|
|
.dbg_hold (r_hold ),
|
.dbg_hold (r_hold ),
|
|
|
.dbg_ll_write_start (0 ),
|
.dbg_ll_write_start (1'b0 ),
|
.dbg_ll_write_data (0 ),
|
.dbg_ll_write_data (32'h0 ),
|
.dbg_ll_write_size (0 ),
|
.dbg_ll_write_size (0 ),
|
.dbg_ll_write_hold (0 ),
|
.dbg_ll_write_hold (1'b0 ),
|
.dbg_ll_write_abort (0 ),
|
.dbg_ll_write_abort (1'b0 ),
|
|
|
|
.dbg_ll_read_ready (1'b0 ),
|
|
.dbg_t_en (1'b0 ),
|
|
|
.dbg_ll_read_ready (0 ),
|
.dbg_send_reg_stb (1'b0 ),
|
.dbg_t_en (0 ),
|
.dbg_send_dma_act_stb (1'b0 ),
|
|
.dbg_send_data_stb (1'b0 ),
|
|
.dbg_send_pio_stb (1'b0 ),
|
|
.dbg_send_dev_bits_stb (1'b0 ),
|
|
|
|
.dbg_pio_transfer_count(16'h0000 ),
|
|
.dbg_pio_direction (1'b0 ),
|
|
.dbg_pio_e_status (8'h00 ),
|
|
|
|
.dbg_d2h_interrupt (1'b0 ),
|
|
.dbg_d2h_notification (1'b0 ),
|
|
.dbg_d2h_status (8'b0 ),
|
|
.dbg_d2h_error (8'b0 ),
|
|
.dbg_d2h_port_mult (4'b0000 ),
|
|
.dbg_d2h_device (8'h00 ),
|
|
.dbg_d2h_lba (48'h000000000000 ),
|
|
.dbg_d2h_sector_count (16'h0000 ),
|
|
|
|
.dbg_cl_if_data (32'b0 ),
|
|
.dbg_cl_if_ready (1'b0 ),
|
|
.dbg_cl_if_size (24'h0 ),
|
|
|
.dbg_send_reg_stb (0 ),
|
.dbg_cl_of_ready (2'b0 ),
|
.dbg_send_dma_act_stb (0 ),
|
.dbg_cl_of_size (24'h0 ),
|
.dbg_send_data_stb (0 ),
|
|
.dbg_send_pio_stb (0 ),
|
|
.dbg_send_dev_bits_stb (0 ),
|
|
|
|
.dbg_pio_transfer_count(0 ),
|
|
.dbg_pio_direction (0 ),
|
|
.dbg_pio_e_status (0 ),
|
|
|
|
.dbg_d2h_interrupt (0 ),
|
|
.dbg_d2h_notification (0 ),
|
|
.dbg_d2h_status (0 ),
|
|
.dbg_d2h_error (0 ),
|
|
.dbg_d2h_port_mult (0 ),
|
|
.dbg_d2h_device (0 ),
|
|
.dbg_d2h_lba (0 ),
|
|
.dbg_d2h_sector_count (0 ),
|
|
|
|
.dbg_cl_if_data (0 ),
|
|
.dbg_cl_if_ready (0 ),
|
|
.dbg_cl_if_size (0 ),
|
|
.dbg_cl_of_ready (0 ),
|
|
.dbg_cl_of_size (0 ),
|
|
.hd_read_from_host (hd_read_from_host ),
|
.hd_read_from_host (hd_read_from_host ),
|
.hd_data_from_host (hd_data_from_host ),
|
.hd_data_from_host (hd_data_from_host ),
|
|
|
|
|
.hd_write_to_host (hd_write_to_host ),
|
.hd_write_to_host (hd_write_to_host ),
|
