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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_acc (clk, rst,
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module oc8051_acc (clk, resetn,
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bit_in, data_in, data2_in,
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bit_in, data_in, data2_in,
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data_out,
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data_out,
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wr, wr_bit, wr_addr,
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wr, wr_bit, wr_addr,
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p, wr_sfr);
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p, wr_sfr);
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input clk, rst, wr, wr_bit, bit_in;
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input clk, resetn, wr, wr_bit, bit_in;
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input [1:0] wr_sfr;
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input [1:0] wr_sfr;
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input [7:0] wr_addr, data_in, data2_in;
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input [7:0] wr_addr, data_in, data2_in;
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output p;
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output p;
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output [7:0] data_out;
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output [7:0] data_out;
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endcase
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endcase
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else
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else
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acc = data_out;
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acc = data_out;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst)
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if (resetn == 1'b0)
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data_out <= #1 `OC8051_RST_ACC;
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data_out <= #1 `OC8051_RST_ACC;
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else
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else
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data_out <= #1 acc;
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data_out <= #1 acc;
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end
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end
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