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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//
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//
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,
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module oc8051_alu_src_sel (clk, resetn, rd, sel1, sel2, sel3,
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acc, ram, pc, dptr,
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acc, ram, pc, dptr,
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op1, op2, op3,
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op1, op2, op3,
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src1, src2, src3);
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src1, src2, src3);
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input clk, rst, rd, sel3;
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input clk, resetn, rd, sel3;
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input [1:0] sel2;
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input [1:0] sel2;
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input [2:0] sel1;
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input [2:0] sel1;
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input [7:0] acc, ram;
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input [7:0] acc, ram;
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input [15:0] dptr;
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input [15:0] dptr;
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input [15:0] pc;
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input [15:0] pc;
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// default: src3= 16'h0;
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// default: src3= 16'h0;
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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op1_r <= #1 8'h00;
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op1_r <= #1 8'h00;
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op2_r <= #1 8'h00;
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op2_r <= #1 8'h00;
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op3_r <= #1 8'h00;
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op3_r <= #1 8'h00;
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end else begin
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end else begin
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op1_r <= #1 op1;
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op1_r <= #1 op1;
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