| Line 16... |
Line 16... |
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// v0.0 - Dinesh A, 5th Jan 2017
|
//// v0.0 - Dinesh A, 5th Jan 2017
|
//// 1. Active edge of reset changed from High to Low
|
//// 1. Active edge of reset changed from High to Low
|
|
//// v0.1 - Dinesh A, 19th Jan 2017
|
|
//// 1. Lint Error fix
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
| Line 100... |
Line 102... |
`OC8051_AS1_OP1: src1 = op1_r;
|
`OC8051_AS1_OP1: src1 = op1_r;
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`OC8051_AS1_OP2: src1 = op2_r;
|
`OC8051_AS1_OP2: src1 = op2_r;
|
`OC8051_AS1_OP3: src1 = op3_r;
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`OC8051_AS1_OP3: src1 = op3_r;
|
`OC8051_AS1_PCH: src1 = pc[15:8];
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`OC8051_AS1_PCH: src1 = pc[15:8];
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`OC8051_AS1_PCL: src1 = pc[7:0];
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`OC8051_AS1_PCL: src1 = pc[7:0];
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// default: src1 = 8'h00;
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default: src1 = 8'h00;
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endcase
|
endcase
|
end
|
end
|
|
|
///////
|
///////
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//
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//
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| Line 138... |
Line 140... |
end
|
end
|
|
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
op1_r <= #1 8'h00;
|
op1_r <= 8'h00;
|
op2_r <= #1 8'h00;
|
op2_r <= 8'h00;
|
op3_r <= #1 8'h00;
|
op3_r <= 8'h00;
|
end else begin
|
end else begin
|
op1_r <= #1 op1;
|
op1_r <= op1;
|
op2_r <= #1 op2;
|
op2_r <= op2;
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op3_r <= #1 op3;
|
op3_r <= op3;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
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