| Line 1317... |
Line 1317... |
// registerd outputs
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// registerd outputs
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|
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <= `OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <= 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= `OC8051_PS_NOT;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <= `OC8051_WRS_N;
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end else if (!wait_data) begin
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end else if (!wait_data) begin
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case (state_dec) /* synopsys parallel_case */
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case (state_dec) /* synopsys parallel_case */
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2'b01: begin
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2'b01: begin
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casex (op_cur) /* synopsys parallel_case */
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_MOVC_DP :begin
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`OC8051_MOVC_DP :begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_OP1;
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src_sel1 <= `OC8051_AS1_OP1;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <= 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
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wr_sfr <= `OC8051_WRS_ACC1;
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end
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end
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`OC8051_MOVC_PC :begin
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`OC8051_MOVC_PC :begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_OP1;
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src_sel1 <= `OC8051_AS1_OP1;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <= 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
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wr_sfr <= `OC8051_WRS_ACC1;
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end
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end
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`OC8051_MOVX_PA : begin
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`OC8051_MOVX_PA : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_OP1;
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src_sel1 <= `OC8051_AS1_OP1;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <= 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
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wr_sfr <= `OC8051_WRS_ACC1;
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end
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end
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`OC8051_MOVX_IA : begin
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`OC8051_MOVX_IA : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_OP1;
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src_sel1 <= `OC8051_AS1_OP1;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= `OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <= `OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <= 1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <= `OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
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wr_sfr <= `OC8051_WRS_ACC1;
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end
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end
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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ram_wr_sel <= #1 `OC8051_RWS_B;
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ram_wr_sel <= `OC8051_RWS_B;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <= `OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <= `OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_DIV;
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alu_op <= `OC8051_ALU_DIV;
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wr <= #1 1'b1;
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wr <= 1'b1;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <= `OC8051_PS_OV;
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wr_sfr <= #1 `OC8051_WRS_ACC2;
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wr_sfr <= `OC8051_WRS_ACC2;
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end
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end
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`OC8051_MUL : begin
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`OC8051_MUL : begin
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ram_wr_sel <= #1 `OC8051_RWS_B;
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ram_wr_sel <= `OC8051_RWS_B;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <= `OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <= `OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_MUL;
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alu_op <= `OC8051_ALU_MUL;
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wr <= #1 1'b1;
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wr <= 1'b1;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <= `OC8051_PS_OV;
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wr_sfr <= #1 `OC8051_WRS_ACC2;
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wr_sfr <=`OC8051_WRS_ACC2;
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end
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end
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default begin
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default begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <=`OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <=`OC8051_WRS_N;
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end
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end
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endcase
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endcase
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <=`OC8051_AS3_DC;
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end
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end
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2'b10: begin
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2'b10: begin
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casex (op_cur) /* synopsys parallel_case */
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_ACALL :begin
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`OC8051_ACALL :begin
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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ram_wr_sel <=`OC8051_RWS_SP;
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src_sel1 <= #1 `OC8051_AS1_PCH;
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src_sel1 <=`OC8051_AS1_PCH;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b1;
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wr <=1'b1;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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`OC8051_LCALL :begin
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`OC8051_LCALL :begin
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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ram_wr_sel <=`OC8051_RWS_SP;
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src_sel1 <= #1 `OC8051_AS1_PCH;
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src_sel1 <=`OC8051_AS1_PCH;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b1;
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wr <=1'b1;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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`OC8051_JBC : begin
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`OC8051_JBC : begin
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ram_wr_sel <= #1 `OC8051_RWS_D;
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ram_wr_sel <=`OC8051_RWS_D;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <=`OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b1;
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wr <=1'b1;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <=`OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_DIV;
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alu_op <=`OC8051_ALU_DIV;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <=`OC8051_PS_OV;
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end
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end
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`OC8051_MUL : begin
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`OC8051_MUL : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <=`OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_MUL;
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alu_op <=`OC8051_ALU_MUL;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <=`OC8051_PS_OV;
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end
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end
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default begin
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default begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <=`OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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endcase
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endcase
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <=`OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <=`OC8051_WRS_N;
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end
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end
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2'b11: begin
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2'b11: begin
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casex (op_cur) /* synopsys parallel_case */
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_RET : begin
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`OC8051_RET : begin
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src_sel1 <= #1 `OC8051_AS1_RAM;
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src_sel1 <=`OC8051_AS1_RAM;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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`OC8051_RETI : begin
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`OC8051_RETI : begin
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src_sel1 <= #1 `OC8051_AS1_RAM;
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src_sel1 <=`OC8051_AS1_RAM;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <=`OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_DIV;
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alu_op <=`OC8051_ALU_DIV;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <=`OC8051_PS_OV;
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end
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end
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`OC8051_MUL : begin
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`OC8051_MUL : begin
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <=`OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_MUL;
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alu_op <=`OC8051_ALU_MUL;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <=`OC8051_PS_OV;
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end
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end
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default begin
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default begin
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <=`OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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end
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end
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endcase
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endcase
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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wr <= #1 1'b0;
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wr <=1'b0;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <=`OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <=`OC8051_WRS_N;
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end
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end
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default: begin
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default: begin
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casex (op_cur) /* synopsys parallel_case */
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_ACALL :begin
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`OC8051_ACALL :begin
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ram_wr_sel <= #1 `OC8051_RWS_SP;
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ram_wr_sel <=`OC8051_RWS_SP;
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src_sel1 <= #1 `OC8051_AS1_PCL;
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src_sel1 <=`OC8051_AS1_PCL;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
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alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b1;
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wr <=1'b1;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <=`OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <=`OC8051_WRS_N;
|
end
|
end
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`OC8051_AJMP : begin
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`OC8051_AJMP : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <=`OC8051_AS2_DC;
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alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_NOT;
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psw_set <=`OC8051_PS_NOT;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
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end
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`OC8051_ADD_R : begin
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`OC8051_ADD_R : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_ADD;
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alu_op <=`OC8051_ALU_ADD;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
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cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
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end
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`OC8051_ADDC_R : begin
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`OC8051_ADDC_R : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <=`OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_ADD;
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alu_op <=`OC8051_ALU_ADD;
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wr <= #1 1'b0;
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wr <=1'b0;
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psw_set <= #1 `OC8051_PS_AC;
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psw_set <=`OC8051_PS_AC;
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cy_sel <= #1 `OC8051_CY_PSW;
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cy_sel <=`OC8051_CY_PSW;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <=`OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_R : begin
|
`OC8051_ANL_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
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cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CJNE_R : begin
|
`OC8051_CJNE_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <=`OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_DEC_R : begin
|
`OC8051_DEC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_R : begin
|
`OC8051_INC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_R : begin
|
`OC8051_MOV_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_AR : begin
|
`OC8051_MOV_AR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DR : begin
|
`OC8051_MOV_DR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CR : begin
|
`OC8051_MOV_CR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_RD : begin
|
`OC8051_MOV_RD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_R : begin
|
`OC8051_ORL_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SUBB_R : begin
|
`OC8051_SUBB_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XCH_R : begin
|
`OC8051_XCH_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <=`OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <=`OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <=`OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XRL_R : begin
|
`OC8051_XRL_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <=`OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
|
|
//op_code [7:1]
|
//op_code [7:1]
|
`OC8051_ADD_I : begin
|
`OC8051_ADD_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_I : begin
|
`OC8051_ADDC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_I : begin
|
`OC8051_ANL_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CJNE_I : begin
|
`OC8051_CJNE_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <=`OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_DEC_I : begin
|
`OC8051_DEC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_I : begin
|
`OC8051_INC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_I : begin
|
`OC8051_MOV_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_ID : begin
|
`OC8051_MOV_ID : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_AI : begin
|
`OC8051_MOV_AI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DI : begin
|
`OC8051_MOV_DI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CI : begin
|
`OC8051_MOV_CI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_IA : begin
|
`OC8051_MOVX_IA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_AI :begin
|
`OC8051_MOVX_AI :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_I : begin
|
`OC8051_ORL_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SUBB_I : begin
|
`OC8051_SUBB_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XCH_I : begin
|
`OC8051_XCH_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <=`OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <=`OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XCHD :begin
|
`OC8051_XCHD :begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <=`OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <=`OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <=`OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XRL_I : begin
|
`OC8051_XRL_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <=`OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
|
|
//op_code [7:0]
|
//op_code [7:0]
|
`OC8051_ADD_D : begin
|
`OC8051_ADD_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADD_C : begin
|
`OC8051_ADD_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_D : begin
|
`OC8051_ADDC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_C : begin
|
`OC8051_ADDC_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_D : begin
|
`OC8051_ANL_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_C : begin
|
`OC8051_ANL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_DD : begin
|
`OC8051_ANL_DD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ANL_DC : begin
|
`OC8051_ANL_DC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <=`OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ANL_B : begin
|
`OC8051_ANL_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <=`OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ANL_NB : begin
|
`OC8051_ANL_NB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RR;
|
alu_op <=`OC8051_ALU_RR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_CJNE_D : begin
|
`OC8051_CJNE_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_CJNE_C : begin
|
`OC8051_CJNE_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <=`OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_CLR_A : begin
|
`OC8051_CLR_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CLR_C : begin
|
`OC8051_CLR_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_CLR_B : begin
|
`OC8051_CLR_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_CPL_A : begin
|
`OC8051_CPL_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
alu_op <=`OC8051_ALU_NOT;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CPL_C : begin
|
`OC8051_CPL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
alu_op <=`OC8051_ALU_NOT;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_CPL_B : begin
|
`OC8051_CPL_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
alu_op <=`OC8051_ALU_NOT;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_RAM;
|
cy_sel <=`OC8051_CY_RAM;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_DA : begin
|
`OC8051_DA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_DA;
|
alu_op <=`OC8051_ALU_DA;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_DEC_A : begin
|
`OC8051_DEC_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_DEC_D : begin
|
`OC8051_DEC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <=`OC8051_ALU_DIV;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <=`OC8051_PS_OV;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_A : begin
|
`OC8051_INC_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_INC_D : begin
|
`OC8051_INC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <=`OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_DP : begin
|
`OC8051_INC_DP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <=`OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <=`OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
wr_sfr <=`OC8051_WRS_DPTR;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JBC :begin
|
`OC8051_JBC :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JC : begin
|
`OC8051_JC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <=`OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNC : begin
|
`OC8051_JNC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNZ :begin
|
`OC8051_JNZ :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_JZ : begin
|
`OC8051_JZ : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <=`OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel1 <=`OC8051_AS1_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_LJMP : begin
|
`OC8051_LJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_D : begin
|
`OC8051_MOV_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_C : begin
|
`OC8051_MOV_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_DA : begin
|
`OC8051_MOV_DA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DD : begin
|
`OC8051_MOV_DD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D3;
|
ram_wr_sel <=`OC8051_RWS_D3;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CD : begin
|
`OC8051_MOV_CD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <=`OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_BC : begin
|
`OC8051_MOV_BC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_RAM;
|
cy_sel <=`OC8051_CY_RAM;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CB : begin
|
`OC8051_MOV_CB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DP : begin
|
`OC8051_MOV_DP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <=`OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <=`OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
wr_sfr <=`OC8051_WRS_DPTR;
|
end
|
end
|
`OC8051_MOVC_DP :begin
|
`OC8051_MOVC_DP :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <=`OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVC_PC : begin
|
`OC8051_MOVC_PC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel1 <=`OC8051_AS1_PCL;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <=`OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_PA : begin
|
`OC8051_MOVX_PA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_AP : begin
|
`OC8051_MOVX_AP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
alu_op <=`OC8051_ALU_MUL;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <=`OC8051_PS_OV;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_D : begin
|
`OC8051_ORL_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ORL_C : begin
|
`OC8051_ORL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ORL_AD : begin
|
`OC8051_ORL_AD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_CD : begin
|
`OC8051_ORL_CD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <=`OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_B : begin
|
`OC8051_ORL_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <=`OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_NB : begin
|
`OC8051_ORL_NB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RL;
|
alu_op <=`OC8051_ALU_RL;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_POP : begin
|
`OC8051_POP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_PUSH : begin
|
`OC8051_PUSH : begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <=`OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_RETI : begin
|
`OC8051_RETI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_RL : begin
|
`OC8051_RL : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RL;
|
alu_op <=`OC8051_ALU_RL;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_RLC : begin
|
`OC8051_RLC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RLC;
|
alu_op <=`OC8051_ALU_RLC;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_RR : begin
|
`OC8051_RR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RR;
|
alu_op <=`OC8051_ALU_RR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_RRC : begin
|
`OC8051_RRC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RRC;
|
alu_op <=`OC8051_ALU_RRC;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SETB_C : begin
|
`OC8051_SETB_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <=`OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_SETB_B : begin
|
`OC8051_SETB_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_SJMP : begin
|
`OC8051_SJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <=`OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_SUBB_D : begin
|
`OC8051_SUBB_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SUBB_C : begin
|
`OC8051_SUBB_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <=`OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <=`OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <=`OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <=`OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SWAP : begin
|
`OC8051_SWAP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <=`OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RLC;
|
alu_op <=`OC8051_ALU_RLC;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <=`OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XCH_D : begin
|
`OC8051_XCH_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <=`OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <=`OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <=`OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XRL_D : begin
|
`OC8051_XRL_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <=`OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XRL_C : begin
|
`OC8051_XRL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <=`OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <=`OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <=`OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XRL_AD : begin
|
`OC8051_XRL_AD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <=`OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <=`OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <=`OC8051_ALU_XOR;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
`OC8051_XRL_CD : begin
|
`OC8051_XRL_CD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <=`OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <=`OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <=`OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <=`OC8051_ALU_XOR;
|
wr <= #1 1'b1;
|
wr <=1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
default: begin
|
default: begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <=`OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <=`OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <=`OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <=`OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <=1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <=`OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <=`OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <=`OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <=`OC8051_WRS_N;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
| Line 2729... |
Line 2729... |
|
|
|
|
//
|
//
|
// remember current instruction
|
// remember current instruction
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) op <= #1 2'b00;
|
if (resetn == 1'b0) op <=2'b00;
|
else if (state==2'b00) op <= #1 op_in;
|
else if (state==2'b00) op <=op_in;
|
|
|
//
|
//
|
// in case of instructions that needs more than one clock set state
|
// in case of instructions that needs more than one clock set state
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
state <= #1 2'b11;
|
state <=2'b11;
|
else if (!mem_wait & !wait_data) begin
|
else if (!mem_wait & !wait_data) begin
|
case (state) /* synopsys parallel_case */
|
case (state) /* synopsys parallel_case */
|
2'b10: state <= #1 2'b01;
|
2'b10: state <=2'b01;
|
2'b11: state <= #1 2'b10;
|
2'b11: state <=2'b10;
|
2'b00:
|
2'b00:
|
casex (op_in) /* synopsys full_case parallel_case */
|
casex (op_in) /* synopsys full_case parallel_case */
|
`OC8051_ACALL : state <= #1 2'b10;
|
`OC8051_ACALL : state <=2'b10;
|
`OC8051_AJMP : state <= #1 2'b10;
|
`OC8051_AJMP : state <=2'b10;
|
`OC8051_CJNE_R : state <= #1 2'b10;
|
`OC8051_CJNE_R : state <=2'b10;
|
`OC8051_CJNE_I : state <= #1 2'b10;
|
`OC8051_CJNE_I : state <=2'b10;
|
`OC8051_CJNE_D : state <= #1 2'b10;
|
`OC8051_CJNE_D : state <=2'b10;
|
`OC8051_CJNE_C : state <= #1 2'b10;
|
`OC8051_CJNE_C : state <=2'b10;
|
`OC8051_LJMP : state <= #1 2'b10;
|
`OC8051_LJMP : state <=2'b10;
|
`OC8051_DJNZ_R : state <= #1 2'b10;
|
`OC8051_DJNZ_R : state <=2'b10;
|
`OC8051_DJNZ_D : state <= #1 2'b10;
|
`OC8051_DJNZ_D : state <=2'b10;
|
`OC8051_LCALL : state <= #1 2'b10;
|
`OC8051_LCALL : state <=2'b10;
|
`OC8051_MOVC_DP : state <= #1 2'b11;
|
`OC8051_MOVC_DP : state <=2'b11;
|
`OC8051_MOVC_PC : state <= #1 2'b11;
|
`OC8051_MOVC_PC : state <=2'b11;
|
`OC8051_MOVX_IA : state <= #1 2'b10;
|
`OC8051_MOVX_IA : state <=2'b10;
|
`OC8051_MOVX_AI : state <= #1 2'b10;
|
`OC8051_MOVX_AI : state <=2'b10;
|
`OC8051_MOVX_PA : state <= #1 2'b10;
|
`OC8051_MOVX_PA : state <=2'b10;
|
`OC8051_MOVX_AP : state <= #1 2'b10;
|
`OC8051_MOVX_AP : state <=2'b10;
|
`OC8051_RET : state <= #1 2'b11;
|
`OC8051_RET : state <=2'b11;
|
`OC8051_RETI : state <= #1 2'b11;
|
`OC8051_RETI : state <=2'b11;
|
`OC8051_SJMP : state <= #1 2'b10;
|
`OC8051_SJMP : state <=2'b10;
|
`OC8051_JB : state <= #1 2'b10;
|
`OC8051_JB : state <=2'b10;
|
`OC8051_JBC : state <= #1 2'b10;
|
`OC8051_JBC : state <=2'b10;
|
`OC8051_JC : state <= #1 2'b10;
|
`OC8051_JC : state <=2'b10;
|
`OC8051_JMP_D : state <= #1 2'b10;
|
`OC8051_JMP_D : state <=2'b10;
|
`OC8051_JNC : state <= #1 2'b10;
|
`OC8051_JNC : state <=2'b10;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNB : state <=2'b10;
|
`OC8051_JNZ : state <= #1 2'b10;
|
`OC8051_JNZ : state <=2'b10;
|
`OC8051_JZ : state <= #1 2'b10;
|
`OC8051_JZ : state <=2'b10;
|
`OC8051_DIV : state <= #1 2'b11;
|
`OC8051_DIV : state <=2'b11;
|
`OC8051_MUL : state <= #1 2'b11;
|
`OC8051_MUL : state <=2'b11;
|
// default : state <= #1 2'b00;
|
default : state <=2'b00;
|
endcase
|
endcase
|
default: state <= #1 2'b00;
|
default: state <=2'b00;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
//in case of writing to external ram
|
//in case of writing to external ram
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
mem_act <= #1 `OC8051_MAS_NO;
|
mem_act <=`OC8051_MAS_NO;
|
end else if (!rd) begin
|
end else if (!rd) begin
|
mem_act <= #1 `OC8051_MAS_NO;
|
mem_act <=`OC8051_MAS_NO;
|
end else
|
end else
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W;
|
`OC8051_MOVX_AI : mem_act <=`OC8051_MAS_RI_W;
|
`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W;
|
`OC8051_MOVX_AP : mem_act <=`OC8051_MAS_DPTR_W;
|
`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R;
|
`OC8051_MOVX_IA : mem_act <=`OC8051_MAS_RI_R;
|
`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R;
|
`OC8051_MOVX_PA : mem_act <=`OC8051_MAS_DPTR_R;
|
`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE;
|
`OC8051_MOVC_DP : mem_act <=`OC8051_MAS_CODE;
|
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE;
|
`OC8051_MOVC_PC : mem_act <=`OC8051_MAS_CODE;
|
default : mem_act <= #1 `OC8051_MAS_NO;
|
default : mem_act <=`OC8051_MAS_NO;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
ram_rd_sel_r <= #1 3'h0;
|
ram_rd_sel_r <=3'h0;
|
end else begin
|
end else begin
|
ram_rd_sel_r <= #1 ram_rd_sel;
|
ram_rd_sel_r <=ram_rd_sel;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
