| Line 15... |
Line 15... |
//// - Simon Teran, simont@opencores.org ////
|
//// - Simon Teran, simont@opencores.org ////
|
//// - Marko Mlinar, markom@opencores.org ////
|
//// - Marko Mlinar, markom@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
//// v0.0 - Dinesh A, 5th Jan 2017
|
|
//// 1. Active edge of reset changed from High to Low
|
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
| Line 50... |
Line 53... |
// prepared header
|
// prepared header
|
//
|
//
|
//
|
//
|
|
|
|
|
module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
|
module oc8051_divide (clk, resetn, enable, src1, src2, des1, des2, desOv);
|
//
|
//
|
// this module is part of alu
|
// this module is part of alu
|
// clk (in)
|
// clk (in)
|
// rst (in)
|
// resetn (in)
|
// enable (in) starts divison
|
// enable (in) starts divison
|
// src1 (in) first operand
|
// src1 (in) first operand
|
// src2 (in) second operand
|
// src2 (in) second operand
|
// des1 (out) first result
|
// des1 (out) first result
|
// des2 (out) second result
|
// des2 (out) second result
|
// desOv (out) Overflow output
|
// desOv (out) Overflow output
|
//
|
//
|
|
|
input clk, rst, enable;
|
input clk, resetn, enable;
|
input [7:0] src1, src2;
|
input [7:0] src1, src2;
|
output desOv;
|
output desOv;
|
output [7:0] des1, des2;
|
output [7:0] des1, des2;
|
|
|
// wires
|
// wires
|
| Line 104... |
Line 107... |
assign rem_out = rem0;
|
assign rem_out = rem0;
|
assign desOv = src2 == 8'h0;
|
assign desOv = src2 == 8'h0;
|
|
|
//
|
//
|
// divider works in four clock cycles -- 0, 1, 2 and 3
|
// divider works in four clock cycles -- 0, 1, 2 and 3
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (rst) begin
|
if (resetn == 1'b0) begin
|
cycle <= #1 2'b0;
|
cycle <= #1 2'b0;
|
tmp_div <= #1 6'h0;
|
tmp_div <= #1 6'h0;
|
tmp_rem <= #1 8'h0;
|
tmp_rem <= #1 8'h0;
|
end else begin
|
end else begin
|
if (enable) cycle <= #1 cycle + 2'b1;
|
if (enable) cycle <= #1 cycle + 2'b1;
|
