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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
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module oc8051_dptr(clk, resetn, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// resetn (in) reset
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// addr (in) write address input [oc8051_ram_wr_sel.out]
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// addr (in) write address input [oc8051_ram_wr_sel.out]
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// data_in (in) destination 1 from alu [oc8051_alu.des1]
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// data_in (in) destination 1 from alu [oc8051_alu.des1]
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// data2_in (in) destination 2 from alu [oc8051_alu.des2]
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// data2_in (in) destination 2 from alu [oc8051_alu.des2]
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// wr (in) write to ram [oc8051_decoder.wr -r]
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// wr (in) write to ram [oc8051_decoder.wr -r]
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// wd2 (in) write from destination 2 [oc8051_decoder.ram_wr_sel -r]
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// wd2 (in) write from destination 2 [oc8051_decoder.ram_wr_sel -r]
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// data_hi (out) output (high bits) [oc8051_alu_src3_sel.dptr, oc8051_ext_addr_sel.dptr_hi, oc8051_ram_sel.dptr_hi]
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// data_hi (out) output (high bits) [oc8051_alu_src3_sel.dptr, oc8051_ext_addr_sel.dptr_hi, oc8051_ram_sel.dptr_hi]
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// data_lo (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
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// data_lo (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
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//
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//
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input clk, rst, wr, wr_bit;
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input clk, resetn, wr, wr_bit;
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input [1:0] wr_sfr;
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input [1:0] wr_sfr;
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input [7:0] addr, data_in, data2_in;
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input [7:0] addr, data_in, data2_in;
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output [7:0] data_hi, data_lo;
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output [7:0] data_hi, data_lo;
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reg [7:0] data_hi, data_lo;
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reg [7:0] data_hi, data_lo;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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data_hi <= #1 `OC8051_RST_DPH;
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data_hi <= #1 `OC8051_RST_DPH;
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data_lo <= #1 `OC8051_RST_DPL;
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data_lo <= #1 `OC8051_RST_DPL;
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end else if (wr_sfr==`OC8051_WRS_DPTR) begin
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end else if (wr_sfr==`OC8051_WRS_DPTR) begin
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//
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//
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//write from destination 2 and 1
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//write from destination 2 and 1
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