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https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_dptr.v] - Diff between revs 25 and 36
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| Rev 25 |
Rev 36 |
| Line 84... |
Line 84... |
reg [7:0] data_hi, data_lo;
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reg [7:0] data_hi, data_lo;
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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data_hi <= #1 `OC8051_RST_DPH;
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data_hi <= `OC8051_RST_DPH;
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data_lo <= #1 `OC8051_RST_DPL;
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data_lo <= `OC8051_RST_DPL;
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end else if (wr_sfr==`OC8051_WRS_DPTR) begin
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end else if (wr_sfr==`OC8051_WRS_DPTR) begin
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//
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//
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//write from destination 2 and 1
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//write from destination 2 and 1
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data_hi <= #1 data2_in;
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data_hi <= data2_in;
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data_lo <= #1 data_in;
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data_lo <= data_in;
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end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
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end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
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//
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//
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//case of writing to dptr
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//case of writing to dptr
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data_hi <= #1 data_in;
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data_hi <= data_in;
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else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit))
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else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit))
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data_lo <= #1 data_in;
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data_lo <= data_in;
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end
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end
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endmodule
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endmodule
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