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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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// prepared header
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// prepared header
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//
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//
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//
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//
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module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
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module oc8051_indi_addr (clk, resetn, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
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//
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//
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input clk, // clock
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input clk, // clock
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rst, // reset
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resetn, // reset
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wr, // write
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wr, // write
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sel, // select register
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sel, // select register
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wr_bit; // write bit addressable
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wr_bit; // write bit addressable
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input [1:0] bank; // select register bank
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input [1:0] bank; // select register bank
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input [7:0] data_in; // data input
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input [7:0] data_in; // data input
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reg [7:0] buff [0:7];
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reg [7:0] buff [0:7];
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//
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//
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//write to buffer
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//write to buffer
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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buff[3'b000] <= #1 8'h00;
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buff[3'b000] <= #1 8'h00;
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buff[3'b001] <= #1 8'h00;
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buff[3'b001] <= #1 8'h00;
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buff[3'b010] <= #1 8'h00;
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buff[3'b010] <= #1 8'h00;
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buff[3'b011] <= #1 8'h00;
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buff[3'b011] <= #1 8'h00;
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buff[3'b100] <= #1 8'h00;
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buff[3'b100] <= #1 8'h00;
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assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
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assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
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data_in : buff[{bank, sel}];
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data_in : buff[{bank, sel}];
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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wr_bit_r <= #1 1'b0;
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wr_bit_r <= #1 1'b0;
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end else begin
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end else begin
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wr_bit_r <= #1 wr_bit;
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wr_bit_r <= #1 wr_bit;
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end
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end
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