| Line 158... |
Line 158... |
//
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//
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// IP
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// IP
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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ip <=#1 `OC8051_RST_IP;
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ip <=`OC8051_RST_IP;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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ip <= #1 data_in;
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ip <= data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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ip[wr_addr[2:0]] <= #1 bit_in;
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ip[wr_addr[2:0]] <= bit_in;
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end
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end
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//
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//
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// IE
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// IE
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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ie <=#1 `OC8051_RST_IE;
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ie <=`OC8051_RST_IE;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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ie <= #1 data_in;
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ie <= data_in;
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
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ie[wr_addr[2:0]] <= #1 bit_in;
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ie[wr_addr[2:0]] <= bit_in;
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end
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end
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//
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//
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// tcon_s
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// tcon_s
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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tcon_s <=#1 4'b0000;
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tcon_s <=4'b0000;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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tcon_s <= {data_in[6], data_in[4], data_in[2], data_in[0]};
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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case (wr_addr[2:0]) /* synopsys full_case parallel_case */
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3'b000: tcon_s[0] <= #1 bit_in;
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3'b000: tcon_s[0] <= bit_in;
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3'b010: tcon_s[1] <= #1 bit_in;
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3'b010: tcon_s[1] <= bit_in;
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3'b100: tcon_s[2] <= #1 bit_in;
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3'b100: tcon_s[2] <= bit_in;
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3'b110: tcon_s[3] <= #1 bit_in;
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3'b110: tcon_s[3] <= bit_in;
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endcase
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endcase
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end
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end
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end
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end
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//
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//
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// tf1 (tmod.7)
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// tf1 (tmod.7)
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
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tcon_tf1 <=#1 1'b0;
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tcon_tf1 <=1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_tf1 <= #1 data_in[7];
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tcon_tf1 <= data_in[7];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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tcon_tf1 <= #1 bit_in;
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tcon_tf1 <= bit_in;
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end else if (!(tf1_buff) & (tf1)) begin
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end else if (!(tf1_buff) & (tf1)) begin
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tcon_tf1 <= #1 1'b1;
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tcon_tf1 <= 1'b1;
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end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
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end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
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tcon_tf1 <= #1 1'b0;
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tcon_tf1 <= 1'b0;
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end
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end
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end
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end
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//
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//
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// tf0 (tmod.5)
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// tf0 (tmod.5)
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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tcon_tf0 <=#1 1'b0;
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tcon_tf0 <=1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_tf0 <= #1 data_in[5];
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tcon_tf0 <= data_in[5];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
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tcon_tf0 <= #1 bit_in;
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tcon_tf0 <= bit_in;
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end else if (!(tf0_buff) & (tf0)) begin
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end else if (!(tf0_buff) & (tf0)) begin
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tcon_tf0 <= #1 1'b1;
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tcon_tf0 <= 1'b1;
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end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
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end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
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tcon_tf0 <= #1 1'b0;
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tcon_tf0 <= 1'b0;
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end
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end
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end
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end
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//
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//
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// ie0 (tmod.1)
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// ie0 (tmod.1)
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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tcon_ie0 <=#1 1'b0;
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tcon_ie0 <=1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_ie0 <= #1 data_in[1];
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tcon_ie0 <= data_in[1];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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tcon_ie0 <= #1 bit_in;
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tcon_ie0 <= bit_in;
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end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
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end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
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tcon_ie0 <= #1 1'b1;
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tcon_ie0 <= 1'b1;
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end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
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end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
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tcon_ie0 <= #1 1'b0;
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tcon_ie0 <= 1'b0;
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end else if (!(tcon_s[0]) & (ie0)) begin
|
end else if (!(tcon_s[0]) & (ie0)) begin
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tcon_ie0 <= #1 1'b0;
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tcon_ie0 <= 1'b0;
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end
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end
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end
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end
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//
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//
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// ie1 (tmod.3)
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// ie1 (tmod.3)
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//
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//
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
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tcon_ie1 <=#1 1'b0;
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tcon_ie1 <=1'b0;
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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tcon_ie1 <= #1 data_in[3];
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tcon_ie1 <= data_in[3];
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
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end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
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tcon_ie1 <= #1 bit_in;
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tcon_ie1 <= bit_in;
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end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
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end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
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tcon_ie1 <= #1 1'b1;
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tcon_ie1 <= 1'b1;
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end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
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end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
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tcon_ie1 <= #1 1'b0;
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tcon_ie1 <= 1'b0;
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end else if (!(tcon_s[1]) & (ie1)) begin
|
end else if (!(tcon_s[1]) & (ie1)) begin
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tcon_ie1 <= #1 1'b0;
|
tcon_ie1 <= 1'b0;
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end
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end
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end
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end
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|
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//
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//
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// interrupt processing
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// interrupt processing
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
int_vec <= #1 8'h00;
|
int_vec <= 8'h00;
|
int_dept <= #1 2'b0;
|
int_dept <= 2'b0;
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isrc[0] <= #1 3'h0;
|
isrc[0] <= 3'h0;
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isrc[1] <= #1 3'h0;
|
isrc[1] <= 3'h0;
|
int_proc <= #1 1'b0;
|
int_proc <= 1'b0;
|
int_lev[0] <= #1 1'b0;
|
int_lev[0] <= 1'b0;
|
int_lev[1] <= #1 1'b0;
|
int_lev[1] <= 1'b0;
|
end else if (reti & int_proc) begin // return from interrupt
|
end else if (reti & int_proc) begin // return from interrupt
|
if (int_dept==2'b01)
|
if (int_dept==2'b01)
|
int_proc <= #1 1'b0;
|
int_proc <= 1'b0;
|
int_dept <= #1 int_dept - 2'b01;
|
int_dept <= int_dept - 2'b01;
|
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
|
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
|
int_proc <= #1 1'b1;
|
int_proc <= 1'b1;
|
int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
|
int_lev[int_dept] <= `OC8051_ILEV_L1;
|
int_dept <= #1 int_dept + 2'b01;
|
int_dept <= int_dept + 2'b01;
|
if (int_l1[0]) begin
|
if (int_l1[0]) begin
|
int_vec <= #1 `OC8051_INT_X0;
|
int_vec <= `OC8051_INT_X0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
|
isrc[int_dept] <= `OC8051_ISRC_IE0;
|
end else if (int_l1[1]) begin
|
end else if (int_l1[1]) begin
|
int_vec <= #1 `OC8051_INT_T0;
|
int_vec <= `OC8051_INT_T0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
|
isrc[int_dept] <= `OC8051_ISRC_TF0;
|
end else if (int_l1[2]) begin
|
end else if (int_l1[2]) begin
|
int_vec <= #1 `OC8051_INT_X1;
|
int_vec <= `OC8051_INT_X1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
|
isrc[int_dept] <= `OC8051_ISRC_IE1;
|
end else if (int_l1[3]) begin
|
end else if (int_l1[3]) begin
|
int_vec <= #1 `OC8051_INT_T1;
|
int_vec <= `OC8051_INT_T1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
|
isrc[int_dept] <= `OC8051_ISRC_TF1;
|
end else if (int_l1[4]) begin
|
end else if (int_l1[4]) begin
|
int_vec <= #1 `OC8051_INT_UART;
|
int_vec <= `OC8051_INT_UART;
|
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
|
isrc[int_dept] <= `OC8051_ISRC_UART;
|
end else if (int_l1[5]) begin
|
end else if (int_l1[5]) begin
|
int_vec <= #1 `OC8051_INT_T2;
|
int_vec <= `OC8051_INT_T2;
|
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
|
isrc[int_dept] <= `OC8051_ISRC_T2;
|
end
|
end
|
|
|
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
|
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
|
int_proc <= #1 1'b1;
|
int_proc <= 1'b1;
|
int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
|
int_lev[int_dept] <= `OC8051_ILEV_L0;
|
int_dept <= #1 2'b01;
|
int_dept <= 2'b01;
|
if (int_l0[0]) begin
|
if (int_l0[0]) begin
|
int_vec <= #1 `OC8051_INT_X0;
|
int_vec <= `OC8051_INT_X0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
|
isrc[int_dept] <= `OC8051_ISRC_IE0;
|
end else if (int_l0[1]) begin
|
end else if (int_l0[1]) begin
|
int_vec <= #1 `OC8051_INT_T0;
|
int_vec <= `OC8051_INT_T0;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
|
isrc[int_dept] <= `OC8051_ISRC_TF0;
|
end else if (int_l0[2]) begin
|
end else if (int_l0[2]) begin
|
int_vec <= #1 `OC8051_INT_X1;
|
int_vec <= `OC8051_INT_X1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
|
isrc[int_dept] <= `OC8051_ISRC_IE1;
|
end else if (int_l0[3]) begin
|
end else if (int_l0[3]) begin
|
int_vec <= #1 `OC8051_INT_T1;
|
int_vec <= `OC8051_INT_T1;
|
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
|
isrc[int_dept] <= `OC8051_ISRC_TF1;
|
end else if (int_l0[4]) begin
|
end else if (int_l0[4]) begin
|
int_vec <= #1 `OC8051_INT_UART;
|
int_vec <= `OC8051_INT_UART;
|
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
|
isrc[int_dept] <= `OC8051_ISRC_UART;
|
end else if (int_l0[5]) begin
|
end else if (int_l0[5]) begin
|
int_vec <= #1 `OC8051_INT_T2;
|
int_vec <= `OC8051_INT_T2;
|
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
|
isrc[int_dept] <= `OC8051_ISRC_T2;
|
end
|
end
|
end else begin
|
end else begin
|
int_vec <= #1 8'h00;
|
int_vec <= 8'h00;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
if (resetn == 1'b0) begin
|
if (resetn == 1'b0) begin
|
tf0_buff <= #1 1'b0;
|
tf0_buff <= 1'b0;
|
tf1_buff <= #1 1'b0;
|
tf1_buff <= 1'b0;
|
ie0_buff <= #1 1'b0;
|
ie0_buff <= 1'b0;
|
ie1_buff <= #1 1'b0;
|
ie1_buff <= 1'b0;
|
end else begin
|
end else begin
|
tf0_buff <= #1 tf0;
|
tf0_buff <= tf0;
|
tf1_buff <= #1 tf1;
|
tf1_buff <= tf1;
|
ie0_buff <= #1 ie0;
|
ie0_buff <= ie0;
|
ie1_buff <= #1 ie1;
|
ie1_buff <= ie1;
|
end
|
end
|
|
|
endmodule
|
endmodule
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