| Line 12... |
Line 12... |
//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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| Line 86... |
Line 88... |
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_memory_interface (clk, rst,
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module oc8051_memory_interface (clk, resetn,
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//decoder
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//decoder
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wr_i,
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wr_i,
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wr_bit_i,
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wr_bit_i,
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rd_sel,
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rd_sel,
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| Line 163... |
Line 165... |
reti
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reti
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);
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);
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input clk,
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input clk,
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rst,
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resetn,
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wr_i,
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wr_i,
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wr_bit_i;
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wr_bit_i;
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input bit_in,
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input bit_in,
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sfr_bit,
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sfr_bit,
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| Line 365... |
Line 367... |
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assign wr_dat = des1;
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assign wr_dat = des1;
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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always @(negedge rst) begin
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always @(negedge resetn) begin
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#5
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#5
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if (ea_rom_sel)
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if (ea_rom_sel)
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$display(" progran execution from external rom");
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$display(" progran execution from external rom");
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else
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else
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$display(" progran execution from internal rom");
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$display(" progran execution from internal rom");
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| Line 431... |
Line 433... |
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
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`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
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// default : wr_addr = 2'bxx;
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// default : wr_addr = 2'bxx;
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst)
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if (resetn == 1'b0)
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rd_ind <= #1 1'b0;
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rd_ind <= #1 1'b0;
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else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
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else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
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rd_ind <= #1 1'b1;
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rd_ind <= #1 1'b1;
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else
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else
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rd_ind <= #1 1'b0;
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rd_ind <= #1 1'b0;
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| Line 459... |
Line 461... |
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//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
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//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
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assign iadr_o = (istb_t) ? iadr_t : pc_out;
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assign iadr_o = (istb_t) ? iadr_t : pc_out;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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iadr_t <= #1 23'h0;
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iadr_t <= #1 23'h0;
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istb_t <= #1 1'b0;
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istb_t <= #1 1'b0;
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imem_wait <= #1 1'b0;
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imem_wait <= #1 1'b0;
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idat_ir <= #1 24'h0;
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idat_ir <= #1 24'h0;
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end else if (mem_act==`OC8051_MAS_CODE) begin
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end else if (mem_act==`OC8051_MAS_CODE) begin
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| Line 488... |
Line 490... |
//
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//
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/////////////////////////////
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/////////////////////////////
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assign dadr_o = dadr_ot;
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assign dadr_o = dadr_ot;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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dwe_o <= #1 1'b0;
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dwe_o <= #1 1'b0;
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dmem_wait <= #1 1'b0;
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dmem_wait <= #1 1'b0;
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dstb_o <= #1 1'b0;
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dstb_o <= #1 1'b0;
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ddat_o <= #1 8'h00;
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ddat_o <= #1 8'h00;
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dadr_ot <= #1 23'h0;
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dadr_ot <= #1 23'h0;
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| Line 542... |
Line 544... |
//
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//
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/////////////////////////////
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/////////////////////////////
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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idat_cur <= #1 32'h0;
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idat_cur <= #1 32'h0;
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idat_old <= #1 32'h0;
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idat_old <= #1 32'h0;
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end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
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end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
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idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
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idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
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idat_old <= #1 idat_cur;
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idat_old <= #1 idat_cur;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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cdata <= #1 8'h00;
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cdata <= #1 8'h00;
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cdone <= #1 1'b0;
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cdone <= #1 1'b0;
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end else if (istb_t) begin
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end else if (istb_t) begin
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cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
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cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
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cdone <= #1 1'b1;
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cdone <= #1 1'b1;
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| Line 650... |
Line 652... |
end
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end
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end
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end
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//
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//
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//in case of reti
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//in case of reti
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) reti <= #1 1'b0;
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if (resetn == 1'b0) reti <= #1 1'b0;
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else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1;
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else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1;
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else reti <= #1 1'b0;
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else reti <= #1 1'b0;
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//
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//
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// remember inputs
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// remember inputs
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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op2_buff <= #1 8'h0;
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op2_buff <= #1 8'h0;
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op3_buff <= #1 8'h0;
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op3_buff <= #1 8'h0;
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end else if (rd) begin
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end else if (rd) begin
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op2_buff <= #1 op2_o;
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op2_buff <= #1 op2_o;
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op3_buff <= #1 op3_o;
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op3_buff <= #1 op3_o;
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| Line 752... |
Line 754... |
end
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end
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assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
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assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
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always @(posedge rst or posedge clk)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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op_pos <= #1 3'h0;
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op_pos <= #1 3'h0;
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end else if (pc_wr_r2) begin
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end else if (pc_wr_r2) begin
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op_pos <= #1 3'h4;// - op_length;////****??????????
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op_pos <= #1 3'h4;// - op_length;////****??????????
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end else if (inc_pc & rd) begin
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end else if (inc_pc & rd) begin
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op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
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op_pos[2] <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
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| Line 769... |
Line 771... |
end
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end
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//
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//
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// remember interrupt
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// remember interrupt
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// we don't want to interrupt instruction in the middle of execution
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// we don't want to interrupt instruction in the middle of execution
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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int_ack_t <= #1 1'b0;
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int_ack_t <= #1 1'b0;
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int_vec_buff <= #1 8'h00;
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int_vec_buff <= #1 8'h00;
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end else if (intr) begin
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end else if (intr) begin
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int_ack_t <= #1 1'b1;
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int_ack_t <= #1 1'b1;
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int_vec_buff <= #1 int_v;
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int_vec_buff <= #1 int_v;
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end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
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end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) int_ack_buff <= #1 1'b0;
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if (resetn == 1'b0) int_ack_buff <= #1 1'b0;
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else int_ack_buff <= #1 int_ack_t;
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else int_ack_buff <= #1 int_ack_t;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) int_ack <= #1 1'b0;
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if (resetn == 1'b0) int_ack <= #1 1'b0;
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else begin
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else begin
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if ((int_ack_buff) & !(int_ack_t))
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if ((int_ack_buff) & !(int_ack_t))
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int_ack <= #1 1'b1;
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int_ack <= #1 1'b1;
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else int_ack <= #1 1'b0;
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else int_ack <= #1 1'b0;
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end
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end
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//
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//
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//interrupt buffer
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//interrupt buffer
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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int_buff1 <= #1 1'b0;
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int_buff1 <= #1 1'b0;
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end else begin
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end else begin
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int_buff1 <= #1 int_buff;
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int_buff1 <= #1 int_buff;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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int_buff <= #1 1'b0;
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int_buff <= #1 1'b0;
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end else if (intr) begin
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end else if (intr) begin
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int_buff <= #1 1'b1;
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int_buff <= #1 1'b1;
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end else if (pc_wait)
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end else if (pc_wait)
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int_buff <= #1 1'b0;
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int_buff <= #1 1'b0;
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| Line 823... |
Line 825... |
pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
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pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
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end else pcs_result = pc + {8'h00, pcs_source};
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end else pcs_result = pc + {8'h00, pcs_source};
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst)
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if (resetn == 1'b0)
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pc <= #1 16'h0;
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pc <= #1 16'h0;
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else if (pc_wr_r2)
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else if (pc_wr_r2)
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pc <= #1 pc_buf;
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pc <= #1 pc_buf;
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else if (rd & !int_ack_t)
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else if (rd & !int_ack_t)
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pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
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pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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pc_buf <= #1 `OC8051_RST_PC;
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pc_buf <= #1 `OC8051_RST_PC;
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end else if (pc_wr) begin
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end else if (pc_wr) begin
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//
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//
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//case of writing new value to pc (jupms)
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//case of writing new value to pc (jupms)
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case (pc_wr_sel) /* synopsys full_case parallel_case */
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case (pc_wr_sel) /* synopsys full_case parallel_case */
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| Line 866... |
Line 868... |
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst)
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if (resetn == 1'b0)
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ddat_ir <= #1 8'h00;
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ddat_ir <= #1 8'h00;
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else if (dack_i)
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else if (dack_i)
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ddat_ir <= #1 ddat_i;
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ddat_ir <= #1 ddat_i;
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////////////////////////
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////////////////////////
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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rn_r <= #1 5'd0;
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rn_r <= #1 5'd0;
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ri_r <= #1 8'h00;
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ri_r <= #1 8'h00;
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imm_r <= #1 8'h00;
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imm_r <= #1 8'h00;
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imm2_r <= #1 8'h00;
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imm2_r <= #1 8'h00;
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rd_addr_r <= #1 1'b0;
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rd_addr_r <= #1 1'b0;
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| Line 899... |
Line 901... |
sp_r <= #1 sp;
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sp_r <= #1 sp;
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pc_wr_r <= #1 pc_wr && (pc_wr_sel != `OC8051_PIS_AH);
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pc_wr_r <= #1 pc_wr && (pc_wr_sel != `OC8051_PIS_AH);
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pc_wr_r2 <= #1 pc_wr_r;
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pc_wr_r2 <= #1 pc_wr_r;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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if (rst) begin
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if (resetn == 1'b0) begin
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inc_pc_r <= #1 1'b1;
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inc_pc_r <= #1 1'b1;
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end else if (istb) begin
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end else if (istb) begin
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inc_pc_r <= #1 inc_pc;
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inc_pc_r <= #1 inc_pc;
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end
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end
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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|
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initial
|
initial
|
begin
|
begin
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wait (!rst)
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wait (!resetn)
|
if (ea_rom_sel) begin
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if (ea_rom_sel) begin
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$display(" ");
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$display(" ");
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$display("\t Program running from internal rom !");
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$display("\t Program running from internal rom !");
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$display(" ");
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$display(" ");
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end else begin
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end else begin
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