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Line 15... |
//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Marko Mlinar, markom@opencores.org ////
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//// - Marko Mlinar, markom@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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// changed to four cycle multiplication, to save resources and
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// changed to four cycle multiplication, to save resources and
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// increase speed
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// increase speed
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module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
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module oc8051_multiply (clk, resetn, enable, src1, src2, des1, des2, desOv);
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//
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//
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// this module is part of alu
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// this module is part of alu
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// clk (in)
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// clk (in)
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// rst (in)
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// resetn (in)
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// enable (in)
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// enable (in)
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// src1 (in) first operand
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// src1 (in) first operand
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// src2 (in) second operand
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// src2 (in) second operand
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// des1 (out) first result
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// des1 (out) first result
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// des2 (out) second result
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// des2 (out) second result
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// desOv (out) Overflow output
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// desOv (out) Overflow output
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//
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//
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input clk, rst, enable;
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input clk, resetn, enable;
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input [7:0] src1, src2;
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input [7:0] src1, src2;
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output desOv;
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output desOv;
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output [7:0] des1, des2;
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output [7:0] des1, des2;
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// wires
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// wires
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assign mul_result = mul_result1 + shifted;
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assign mul_result = mul_result1 + shifted;
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assign des1 = mul_result[15:8];
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assign des1 = mul_result[15:8];
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assign des2 = mul_result[7:0];
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assign des2 = mul_result[7:0];
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assign desOv = | des1;
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assign desOv = | des1;
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst) begin
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if (resetn == 1'b0) begin
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cycle <= #1 2'b0;
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cycle <= #1 2'b0;
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tmp_mul <= #1 16'b0;
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tmp_mul <= #1 16'b0;
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end else begin
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end else begin
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if (enable) cycle <= #1 cycle + 2'b1;
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if (enable) cycle <= #1 cycle + 2'b1;
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tmp_mul <= #1 mul_result;
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tmp_mul <= #1 mul_result;
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