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Line 16... |
//// - Dinesh Annayya, simont@opencores.org ////
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//// - Dinesh Annayya, simont@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//// 1. Active edge of reset changed from High to Low
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//// v0.1 - Dinesh A, 19th Jan 2017
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//// 1. Lint Warning fixes
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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| Line 153... |
Line 155... |
// case of writing to port
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// case of writing to port
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0) begin
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if (resetn == 1'b0) begin
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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p0_out <= #1 `OC8051_RST_P0;
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p0_out <= `OC8051_RST_P0;
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`endif
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`endif
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|
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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p1_out <= #1 `OC8051_RST_P1;
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p1_out <= `OC8051_RST_P1;
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`endif
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`endif
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|
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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p2_out <= #1 `OC8051_RST_P2;
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p2_out <= `OC8051_RST_P2;
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`endif
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`endif
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|
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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p3_out <= #1 `OC8051_RST_P3;
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p3_out <= `OC8051_RST_P3;
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`endif
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`endif
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end else if (wr) begin
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end else if (wr) begin
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if (!wr_bit) begin
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if (!wr_bit) begin
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case (wr_addr) /* synopsys full_case parallel_case */
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case (wr_addr) /* synopsys full_case parallel_case */
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//
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//
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// bytaddresable
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// bytaddresable
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_P0: begin p0_out <= #1 data_in;
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`OC8051_SFR_P0: begin p0_out <= data_in;
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end
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end
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`endif
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`endif
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|
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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`OC8051_SFR_P1: p1_out <= #1 data_in;
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`OC8051_SFR_P1: p1_out <= data_in;
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`endif
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`endif
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|
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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`OC8051_SFR_P2: p2_out <= #1 data_in;
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`OC8051_SFR_P2: p2_out <= data_in;
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`endif
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`endif
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|
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`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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`OC8051_SFR_P3: p3_out <= #1 data_in;
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`OC8051_SFR_P3: p3_out <= data_in;
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`endif
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`endif
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endcase
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endcase
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end else begin
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end else begin
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case (wr_addr[7:3]) /* synopsys full_case parallel_case */
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case (wr_addr[7:3]) /* synopsys full_case parallel_case */
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|
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//
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//
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// bit addressable
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// bit addressable
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= bit_in;
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`endif
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`endif
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|
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`ifdef OC8051_PORT1
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`ifdef OC8051_PORT1
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= bit_in;
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`endif
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`endif
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|
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`ifdef OC8051_PORT2
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`ifdef OC8051_PORT2
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= bit_in;
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`endif
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`endif
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|
|
`ifdef OC8051_PORT3
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`ifdef OC8051_PORT3
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
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`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= bit_in;
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`endif
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`endif
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default: begin
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`ifdef OC8051_PORT0
|
|
p0_out <= `OC8051_RST_P0;
|
|
`endif
|
|
|
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`ifdef OC8051_PORT1
|
|
p1_out <= `OC8051_RST_P1;
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT2
|
|
p2_out <= `OC8051_RST_P2;
|
|
`endif
|
|
|
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`ifdef OC8051_PORT3
|
|
p3_out <= `OC8051_RST_P3;
|
|
`endif
|
|
end
|
endcase
|
endcase
|
end
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end
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end
|
end
|
end
|
end
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