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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya , dinesha@opencores.org ////
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//// - Dinesh Annayya , dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// v0.0 - Dinesh A, 5th Jan 2017
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//// 1. Active edge of reset changed from High to Low
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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`include "top_defines.v"
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`include "top_defines.v"
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module oc8051_psw (clk, rst, wr_addr, data_in, wr, wr_bit, data_out, p,
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module oc8051_psw (clk, resetn, wr_addr, data_in, wr, wr_bit, data_out, p,
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cy_in, ac_in, ov_in, set, bank_sel);
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cy_in, ac_in, ov_in, set, bank_sel);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// resetn (in) reset
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// data_in (in) data input [oc8051_alu.des1]
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// data_in (in) data input [oc8051_alu.des1]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// p (in) parity [oc8051_acc.p]
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// p (in) parity [oc8051_acc.p]
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// ov_in (in) overflov input [oc8051_alu.desOv]
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// ov_in (in) overflov input [oc8051_alu.desOv]
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// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
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// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
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//
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//
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input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
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input clk, resetn, wr, p, cy_in, ac_in, ov_in, wr_bit;
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input [1:0] set;
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input [1:0] set;
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input [7:0] wr_addr, data_in;
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input [7:0] wr_addr, data_in;
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output [1:0] bank_sel;
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output [1:0] bank_sel;
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output [7:0] data_out;
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output [7:0] data_out;
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assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
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assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
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assign data_out = {data[7:1], p};
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assign data_out = {data[7:1], p};
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//
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//
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//case writing to psw
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//case writing to psw
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always @(posedge clk or posedge rst)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (rst)
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if (resetn == 1'b0)
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data <= #1 `OC8051_RST_PSW;
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data <= #1 `OC8051_RST_PSW;
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//
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//
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// write to psw (byte addressable)
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// write to psw (byte addressable)
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else begin
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else begin
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