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https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_psw.v] - Diff between revs 25 and 36
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| Rev 25 |
Rev 36 |
| Line 104... |
Line 104... |
//
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//
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//case writing to psw
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//case writing to psw
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always @(posedge clk or negedge resetn)
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always @(posedge clk or negedge resetn)
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begin
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begin
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if (resetn == 1'b0)
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if (resetn == 1'b0)
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data <= #1 `OC8051_RST_PSW;
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data <= `OC8051_RST_PSW;
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//
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//
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// write to psw (byte addressable)
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// write to psw (byte addressable)
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else begin
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else begin
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if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
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if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
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data[7:1] <= #1 data_in[7:1];
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data[7:1] <= data_in[7:1];
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//
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//
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// write to psw (bit addressable)
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// write to psw (bit addressable)
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else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
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else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
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data[wr_addr[2:0]] <= #1 cy_in;
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data[wr_addr[2:0]] <= cy_in;
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else begin
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else begin
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case (set) /* synopsys full_case parallel_case */
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case (set) /* synopsys full_case parallel_case */
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`OC8051_PS_CY: begin
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`OC8051_PS_CY: begin
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//
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//
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//write carry
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//write carry
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data[7] <= #1 cy_in;
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data[7] <= cy_in;
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end
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end
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`OC8051_PS_OV: begin
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`OC8051_PS_OV: begin
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//
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//
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//write carry and overflov
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//write carry and overflov
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data[7] <= #1 cy_in;
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data[7] <= cy_in;
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data[2] <= #1 ov_in;
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data[2] <= ov_in;
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end
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end
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`OC8051_PS_AC:begin
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`OC8051_PS_AC:begin
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//
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//
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//write carry, overflov and ac
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//write carry, overflov and ac
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data[7] <= #1 cy_in;
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data[7] <= cy_in;
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data[6] <= #1 ac_in;
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data[6] <= ac_in;
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data[2] <= #1 ov_in;
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data[2] <= ov_in;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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