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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_256x8_two_bist.v] - Diff between revs 20 and 25

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Rev 20	Rev 25
Line 14...	Line 14...
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
`//// - Dinesh Annayya, dinesha@opencores.org ////`	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
	`//// v0.0 - Dinesh A, 5th Jan 2017`
	`//// 1. Active edge of reset changed from High to Low`
	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
Line 54...	Line 57...
`//`	`//`
`// two port ram`	`// two port ram`
`//`	`//`
`module oc8051_ram_256x8_two_bist (`	`module oc8051_ram_256x8_two_bist (`
`clk,`	`clk,`
`rst,`	`resetn,`
`rd_addr,`	`rd_addr,`
`rd_data,`	`rd_data,`
`rd_en,`	`rd_en,`
`wr_addr,`	`wr_addr,`
`wr_data,`	`wr_data,`
Line 75...	Line 78...
`);`	`);`


`input clk,`	`input clk,`
`wr,`	`wr,`
`rst,`	`resetn,`
`rd_en,`	`rd_en,`
`wr_en;`	`wr_en;`
`input [7:0] wr_data;`	`input [7:0] wr_data;`
`input [7:0] rd_addr,`	`input [7:0] rd_addr,`
`wr_addr;`	`wr_addr;`
Line 96...	Line 99...

`ifdef OC8051_RAM_XILINX	`ifdef OC8051_RAM_XILINX
`xilinx_ram_dp u_ram(`	`xilinx_ram_dp u_ram(`
`// read port`	`// read port`
`.CLKA(clk),`	`.CLKA(clk),`
`.RSTA(rst),`	`.RSTA(resetn),`
`.ENA(rd_en),`	`.ENA(rd_en),`
`.ADDRA(rd_addr),`	`.ADDRA(rd_addr),`
`.DIA(8'h00),`	`.DIA(8'h00),`
`.WEA(1'b0),`	`.WEA(1'b0),`
`.DOA(rd_data),`	`.DOA(rd_data),`

`// write port`	`// write port`
`.CLKB(clk),`	`.CLKB(clk),`
`.RSTB(rst),`	`.RSTB(resetn),`
`.ENB(wr_en),`	`.ENB(wr_en),`
`.ADDRB(wr_addr),`	`.ADDRB(wr_addr),`
`.DIB(wr_data),`	`.DIB(wr_data),`
`.WEB(wr),`	`.WEB(wr),`
`.DOB()`	`.DOB()`
Line 123...	Line 126...

`elsif OC8051_RAM_ACTEL	`elsif OC8051_RAM_ACTEL

`oc8051_actel_ram_256x8 u_ram(`	`oc8051_actel_ram_256x8 u_ram(`
`.RWCLK ( clk ),`	`.RWCLK ( clk ),`
`.RESET ( rst ),`	`.RESET ( resetn ),`
`.REN ( rd_en ),`	`.REN ( rd_en ),`
`.RADDR ( rd_addr ),`	`.RADDR ( rd_addr ),`
`.RD ( rd_data ),`	`.RD ( rd_data ),`

`.WEN ( wr ),`	`.WEN ( wr ),`
Line 138...	Line 141...

`elsif OC8051_RAM_GENERIC	`elsif OC8051_RAM_GENERIC

`generic_dpram #(8, 8) u_ram(`	`generic_dpram #(8, 8) u_ram(`
`.rclk ( clk ),`	`.rclk ( clk ),`
`.rrst ( rst ),`	`.rresetn( resetn ),`
`.rce ( rd_en ),`	`.rce ( rd_en ),`
`.oe ( 1'b1 ),`	`.oe ( 1'b1 ),`
`.raddr ( rd_addr ),`	`.raddr ( rd_addr ),`
`.do ( rd_data ),`	`.do ( rd_data ),`

`.wclk ( clk ),`	`.wclk ( clk ),`
`.wrst ( rst ),`	`.wresetn ( resetn ),`
`.wce ( wr_en ),`	`.wce ( wr_en ),`
`.we ( wr ),`	`.we ( wr ),`
`.waddr ( wr_addr ),`	`.waddr ( wr_addr ),`
`.di ( wr_data )`	`.di ( wr_data )`
`);`	`);`
Line 170...	Line 173...
`buff[wr_addr] <= #1 wr_data;`	`buff[wr_addr] <= #1 wr_data;`
`end`	`end`

`//`	`//`
`// reading from ram`	`// reading from ram`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or negedge resetn)`
`begin`	`begin`
`if (rst)`	`if (resetn == 1'b0)`
`rd_data <= #1 8'h0;`	`rd_data <= #1 8'h0;`
`else if ((wr_addr==rd_addr) & wr & rd_en)`	`else if ((wr_addr==rd_addr) & wr & rd_en)`
`rd_data <= #1 wr_data;`	`rd_data <= #1 wr_data;`
`else if (rd_en)`	`else if (rd_en)`
`rd_data <= #1 buff[rd_addr];`	`rd_data <= #1 buff[rd_addr];`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_256x8_two_bist.v] - Diff between revs 20 and 25