URL
https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk
[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Diff between revs 25 and 36
Show entire file |
Details |
Blame |
View Log
| Rev 25 |
Rev 36 |
| Line 164... |
Line 164... |
reg [31:0] buff [0:(1<<ADR_WIDTH) -1];
|
reg [31:0] buff [0:(1<<ADR_WIDTH) -1];
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
dat1_o <= #1 32'h0;
|
dat1_o <= 32'h0;
|
else if (wr1) begin
|
else if (wr1) begin
|
buff[adr1] <= #1 dat1_i;
|
buff[adr1] <= dat1_i;
|
dat1_o <= #1 dat1_i;
|
dat1_o <= dat1_i;
|
end else
|
end else
|
dat1_o <= #1 buff[adr1];
|
dat1_o <= buff[adr1];
|
end
|
end
|
|
|
always @(posedge clk or negedge resetn)
|
always @(posedge clk or negedge resetn)
|
begin
|
begin
|
if (resetn == 1'b0)
|
if (resetn == 1'b0)
|
dat0_o <= #1 32'h0;
|
dat0_o <= 32'h0;
|
else if ((adr0==adr1) & wr1)
|
else if ((adr0==adr1) & wr1)
|
dat0_o <= #1 dat1_i;
|
dat0_o <= dat1_i;
|
else
|
else
|
dat0_o <= #1 buff[adr0];
|
dat0_o <= buff[adr0];
|
end
|
end
|
|
|
`endif //OC8051_RAM_GENERIC
|
`endif //OC8051_RAM_GENERIC
|
`endif //OC8051_RAM_VIRTUALSILICON
|
`endif //OC8051_RAM_VIRTUALSILICON
|
`endif //OC8051_RAM_XILINX
|
`endif //OC8051_RAM_XILINX
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.